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dbcool remote thermal monitor and fan controller with peci interface adt7490 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features temperature measurement: 1 local on-chip temperature sensor 2 remote temperature sensors 3-current external temperature sensors with series resistance cancellation (src) peci interface for cpu thermal information and support of up to 4 peci inputs on one pin fan drive and fan speed control 3 high frequency or low frequency pwm outputs for use with 3-wire or 4-wire fans 4 tach inputs to measure fan speed os independent automatic fan speed control based on thermal information dynamic t min control mode to optimize system acoustics default startup at 100% pwm for all fans for robust operation bidirectional therm / smbalert pin to flag out-of-limit and overtemperature conditions gpio functionality to support extra features can be used for loadline setting for voltage regulation, led control, or other functions i mon monitoring for cpu current and power information footprint and register compatible with adt7473/adt7475/ adt7476/adt7476a family of fan controllers smbus interface with addressing capability for up to 3 devices applications personal computers servers general description the adt7490 is a db cool? thermal monitor and multiple pwm fan controller for noise-sensitive or power-sensitive applications requiring active system cooling. the adt7490 includes a local temperature sensor, two remote temperature sensors including series resistance cancellation, and monitors cpu temperature with a peci interface. the adt7490 can drive a fan using either a low or high frequency drive signal, and measure and control the speed of up to four fans so they operate at the lowest possible speed for minimum acoustic noise. the automatic fan speed control loop optimizes fan speed for a given temperature using the peci, remote, or local temperature information. the effectiveness of the systems thermal solution can be monitored using the therm input. the adt7490 also provides critical thermal protection to the system using the bidirectional therm / smbalert pin as an output to prevent system or component overheating.
adt7490 rev. 0 | page 2 of 76 functional block diagram acoustic enhancement control band gap reference 10-bit adc interrupt masking pwm configuration registers address pointer register value and limit registers limit comparators interrupt status registers input signal conditioning and analog multiplexer v cc v tt d1+ d1? d2+ d2? peci serial bus interface sc l sda s mbalert smbus address selection addr select gnd pwm1 pwm2 automatic fan speed control tach3 tach4 fan speed counter thermal protection performance monitoring therm/ band gap temp. sensor adt7490 peci interface +12v in +5v in +2.5v in v ccp pwm3 pwm registers and controllers (hf and lf) tach1 tach2 i mon gpio register gpio1 gpio2 dynamic t min control acoustic enhancement 06789-001 figure 1.
adt7490 rev. 0 | page 3 of 76 table of contents features...............................................................................................1 applications .......................................................................................1 general description..........................................................................1 functional block diagram ...............................................................2 revision history................................................................................3 specifications .....................................................................................4 absolute maximum ratings ............................................................6 thermal characteristics...............................................................6 esd caution ..................................................................................6 pin configuration and function descriptions .............................7 typical performance characteristics ..............................................9 theory of operation .......................................................................12 feature comparisons between the adt7490 and adt7476a .......................................................................................................12 start-up operation .....................................................................13 serial bus interface .....................................................................13 write operations.........................................................................14 read operations..........................................................................15 smbus timeout...........................................................................16 voltage measurement input.......................................................16 additional adc functions for voltage measurements.........17 temperature measurement........................................................19 thermal diode temperature measurement method.............21 series resistance cancellation ..................................................22 factors affecting diode accuracy............................................22 additional adc functions for temperature measurement .23 limits, status registers, and interrupts .......................................25 limit values .................................................................................25 interrupt status registers...........................................................26 therm timer ............................................................................28 fan drive using pwm control ................................................30 laying out 3-wire fans.............................................................32 programming t range .....................................................................35 programming the automatic fan speed control loop ..............36 manual fan control overview .................................................36 therm operation in manual mode.......................................36 automatic fan control overview ............................................36 step 1: hardware configuration ...............................................37 step 2: configuring the muxtiplexer........................................37 step 3: t min settings for thermal calibration channels .......38 step 4: pwm min for each pwm (fan) output .......................40 step 5: pwm max for pwm (fan) outputs...............................40 step 6: t range for temperature channels ................................41 step 7: t therm for temperature channels ................................43 step 8: t hyst for temperature channels...................................44 programming the gpios ...........................................................46 xnor tree test mode ...............................................................46 register tables .................................................................................47 outline dimensions........................................................................76 ordering guide ...........................................................................76 revision history 7/07revision 0: initial version
adt7490 rev. 0 | page 4 of 76 specifications t a = t min to t max , v cc = v min to v max , unless otherwise noted. all voltages are measured with respect to gnd, unless otherwise specified. typical voltages are t a = 25c and represent a parametric norm. logic inputs accept input high voltages up to v max , even when the device is operating down to v min . timing specifications are tested at logic levels of v il = 0.8 v for a falling edge, and v ih = 2.0 v for a rising edge. table 1. parameter min typ max unit test conditions/comments power supply supply voltage 3.0 3.3 3.6 v supply current, i cc 1.5 5 ma interface inactive, adc active temperature-to-digital converter local sensor accuracy 0.5 1.5 c 0c t a 85c 2.5 c ?40c t a +125c resolution 0.25 c remote diode sensor accuracy 0.5 1.5 c 0c t a 85c 2.5 c ?40c t a +125c resolution 0.25 c remote sensor source current 12 a low level 72 a mid level 192 ? high level series resistance cancellation 1 1.5 k the adt7490 cancels up to 2 k in series with the remote thermal sensor analog-to-digital converter (including mux and attentuators) total unadjusted error (tue) 2 % for all channels: ?40c t a +125c 1.5 % for all other channels except +12v in : 0c t a +125c differential nonlinearity (dnl) 1 lsb 8 bits power supply sensitivity 0.1 %/v conversion times 1 voltage inputs 11 13 ms averaging enabled, all channels excluding v tt 2 v tt voltage input 2 12 14 ms averaging enabled local temperature 12 14 ms averaging enabled remote temperature 38 43 ms averaging enabled total monitoring cycle time 169 193 ms averaging enabled 19 ms averaging disabled input resistance 150 200 k for +12v in channel 70 100 k for all other channels fan rpm-to-digital converter accuracy 10 % 0c t a 85c 14 % ?40c t a +125c full-scale count 65,535 nominal input rpm 109 rpm fan count = 0xbfff 329 rpm fan count = 0x3fff 5000 rpm fan count = 0x0438 10,000 rpm fan count = 0x021c open-drain digital outputs, pwm1 to pwm3, xto current sink, i ol 8.0 ma output low voltage, v ol 0.4 v i out = ?8.0 ma high level output current, i oh 0.1 20 a v out = v cc
adt7490 rev. 0 | page 5 of 76 parameter min typ max unit test conditions/comments open-drain serial data bus output (sda) output low voltage, v ol 0.4 v i out = ?4.0 ma high level output current, i oh 0.1 1.0 a v out = v cc smbus digital inputs (scl, sda) input high voltage, v ih 2.0 v input low voltage, v il 0.4 v hysteresis 500 mv digital i/o (peci pin) 1 0.95 1.26 v v tt, supply voltage input high voltage , v ih 0.55 v tt 2 v input low voltage, v il 0.5 v tt 2 v hysteresis 1 0.1 v tt 2 mv hysteresis between input switching levels high level output source current, i source 6 ma v oh = 0.75 v tt low level output sink current, i sink 0.5 1.0 ma v ol = 0.25 v tt signal noise immunity, v noise 300 mv p-p noise glitches from 10 mhz to 100 mhz, width up to 50 ns digital input logic levels (tach1 to tach3) input high voltage, v ih 2.0 v 5.5 v maximum input voltage input low voltage, v il 0.8 v ?0.3 v minimum input voltage hysteresis 0.5 v p-p digital input logic levels ( therm ) input high voltage, v ih 0.75 v cc v input low voltage, v il 0.4 v digital input current input high current, i ih 1 a v in = v cc input low current, i il 1 a v in = 0 input capacitance, c in 5 pf serial bus timing 1 see figure 2 clock frequency, f sclk 10 400 khz glitch immunity, t sw 50 ns bus free time, t buf 4.7 s scl low time, t low 4.7 s scl high time, t high 4.0 50 s scl, sda rise time, t r 1000 ns scl, sda fall time, t f 300 s data setup time, t su;dat 250 ns detect clock low timeout, t timeout 15 35 ms can be optionally disabled 1 guaranteed by design, not production tested. 2 v tt is the voltage input on pin 8. the v tt voltage is determined by the processor installed on the system. scl sda ps sp t buf t hd;sta t hd;dat t su;dat t f t r t low t su;sta t high t hd;sta t su;sto 06789-002 figure 2. smbus timing diagram
adt7490 rev. 0 | page 6 of 76 absolute maximum ratings table 2. parameter rating positive supply voltage (v cc ) 3.6 v maximum voltage on +12v in pin 16 v maximum voltage on +5v in pin 6.25 v maximum voltage on all open-drain outputs 3.6 v maximum voltage on tachx/pwmx pins +5.5 v voltage on remaining input or output pins ?0.3 v to +4.2 v input current at any pin 5 ma package input current 20 ma maximum junction temperature (t j max ) 150c storage temperature range ?65c to +150c lead temperature, soldering ir reflow peak temperature 220c pb-free peak temperature 260c lead temperature (soldering, 10 sec) 300c esd rating hbm 2 kv ficdm 0.5 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics 24-lead qsop package: table 3. thermal resistance package type ja unit ja 122 c/w jc 31.25 c/w esd caution
adt7490 rev. 0 | page 7 of 76 pin configuration and fu nction descriptions 06789-003 d1? d2+ d2? tach4/therm/smbalert/addr select +5v in +12v in +2.5v in /therm v ccp i mon d1+ 16 9 15 10 14 11 13 12 tach1 tach2 pwm3/addren 20 5 19 6 18 7 17 8 gnd v cc gpio1 tach3 v tt peci gpio2 21 4 22 3 23 2 scl pwm1/xto 24 1 sda pwm2/smbalert adt7490 top view (not to scale) figure 3.pin configuration table 4. pin function descriptions pin no. mnemonic type description 1 sda digital i/o smbus bidirectional serial data. open drain, requires smbus pull-up. 2 scl digital input smbus serial clock inp ut. open drain, requires smbus pull-up. 3 gnd ground ground pin. 4 v cc power supply 3.3 v 10%. 5 gpio1 digital input/output general-purpose open-drain digital input/ output. frequently used for switching loadline resistors into vr loadline circuitry or for switching leds using external fets. 6 gpio2 digital input/output general-purpose open-drain digital input/ output. frequently used for switching loadline resistors into vr loadline circuitry or for switching leds using external fets. 7 peci digital input peci input to report cpu thermal information. peci voltage level is referenced on the v tt input 8 v tt analog input voltage reference for peci. this is the supply voltage for the peci interface and must be present to measure temperature over the peci interface. this voltage is also monitored and presented in register 0x1e. 9 tach3 digital input fan tachometer input to me asure speed of fan 3 (open-drain digital input). 10 pwm2/ digital output pulse width modulated output to control fan 2 speed. open drain requires 10 k typical pull-up. smbalert digital output (open drain). this pin can be reconfigured as an smbalert interrupt output to signal out-of-limit conditions. 11 tach1 digital input fan tachometer input to measure speed of fan 1 (open-drain digital input.). 12 tach2 digital input fan tachometer input to measure speed of fan 2 (open-drain digital input.). 13 pwm3/ digital output pulse width modulated output to control fan 3 speed. open drain requires 10k typical pull-up. addren if pulled low on power-up, the adt7490 enters address select mode, and the state of pin 14 ( addr select ) determines the adt7490s slave address. 14 tach4/ digital input/output fan tachometer input to measure speed of fan 4 (open-drain digital input). therm / may be reconfigured as a bidirectional therm pin. can be connected to prochot output of processor, to time and monitor prochot assertions. can be used as an output to signal overtemperature conditio ns or for clock modulation purposes. smbalert / active low digital output. the smbalert pin is used to signal out-of-limit comparisons of temperature, voltage, and fan speed. this is compatible with smbus alert. addr select can also be used at device power-up to assign smbus address. 15 d2? analog input negative connection for remote temperature sensor 2. 16 d2+ analog input positive connection to remote temperature sensor 2. 17 d1? analog input negative connection for remote temperature sensor 1. 18 d1+ analog input positive connection to remote temperature sensor 1. 19 i mon analog input monitors current output of analog devices adp319x family of vrd10/vrd11 controllers.
adt7490 rev. 0 | page 8 of 76 pin no. mnemonic type description 20 +5v in analog input monitors 5 v supply using internal resistor dividers. 21 +12v in analog input monitors 12 v supply using internal resistor dividers. 22 +2.5v in / analog input monitors 2.5 v supply using internal resistor dividers. therm alternatively, this pin can be reconfigured as a bidirectional therm pin. can be connected to prochot output of processor to time and monitor prochot assertions. can be used as an output to signal overtemp erature conditions or for clock modulation purposes. 23 v ccp analog input monitors cpu v cc voltage (to maximum of 3.0 v). all voltage inputs can have their resistor dividers removed allowing for full-scale input of 2.25 v of adc channel. 24 pwm1/ digital output pulse width modulated output to control fan 1 speed. open drain requires 10 k typical pull-up. xto also functions as the output for the xnor tree test enable mode. table 5. comparison of adt 7490 and adt7476a configurations pin number adt7490 adt7476a 1 sda sda 2 scl scl 3 gnd gnd 4 v cc v cc 5 gpio1 vid0/gpio0 6 gpio2 vid1/gpio1 7 peci vid2/gpio2 8 v tt vid3/gpio3 9 tach3 tach3 10 pwm2/ smbalert pwm2/ smbalert 11 tach1 tach1 12 tach2 tach2 13 pwm3/ addren pwm3/ addren 14 tach4/ therm / smbalert / addr select tach4/ therm / smbalert /gpio6/ addr select 15 d2? d2? 16 d2+ d2+ 17 d1? d1? 18 d1+ d1+ 19 i mon vid4/gpio4 20 +5v in +5v in 21 +12v in +12v in /vid5 22 +2.5v in / therm +2.5v in / therm 23 v ccp v ccp 24 pwm1/xto pwm1/xto
adt7490 rev. 0 | page 9 of 76 typical performance characteristics 3.5 3.7 3.9 4.1 4.3 4.5 4.7 3.0 3.1 3.2 3.3 3.4 3.5 3.6 normal i dd (ma) v dd (v) dev 3 dev 2 dev 1 0 6789-006 figure 4. supply current vs. supply voltage ?40 ?20 0 20 40 60 80 100 120 normal i dd (ma) temperature (c) 4.12 4.14 4.16 4.18 4.20 4.22 4.24 dev 2 dev 1 dev 3 06789-007 figure 5. supply current vs. temperature 06789-008 temperature error (c) temperature (c) dev 1 dev 2 dev 3 dev 4 dev 5 dev 6 dev 7 dev 8 dev 9 dev 10 dev 11 dev 12 dev 13 dev 14 dev 15 dev 16 dev 17 dev 18 dev 19 dev 20 dev 21 dev 22 dev 23 dev 24 dev 25 dev 26 dev 27 dev 28 dev 29 dev 30 dev 31 dev 32 mean low spec high spec ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 ?40 ?20 0 25 40 60 70 85 100 125 ?1.5 figure 6. local temperature sensor error ?40 ?20 0 25 40 60 70 85 100 125 06789-009 temperature error (c) temperature (c) dev 1 dev 2 dev 3 dev 4 dev 5 dev 6 dev 7 dev 8 dev 9 dev 10 dev 11 dev 12 dev 13 dev 14 dev 15 dev 16 dev 17 dev 18 dev 19 dev 20 dev 21 dev 22 dev 23 dev 24 dev 25 dev 26 dev 27 dev 28 dev 29 dev 30 dev 31 dev 32 mean low spec high spec ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 figure 7. remote 1 temperature sensor error ?40 ?20 0 25 40 60 70 85 100 125 06789-010 temperature error (c) temperature (c) dev 1 dev 2 dev 3 dev 4 dev 5 dev 6 dev 7 dev 8 dev 9 dev 10 dev 11 dev 12 dev 13 dev 14 dev 15 dev 16 dev 17 dev 18 dev 19 dev 20 dev 21 dev 22 dev 23 dev 24 dev 25 dev 26 dev 27 dev 28 dev 29 dev 30 dev 31 dev 32 mean low spec high spec ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 figure 8. remote 2 temperature sensor error local 140 0 20 40 60 80 100 120 0 10203040506 06789-072 measured temperature (c) time (s) 0 external 1 external 2 figure 9. adt7490 response to thermal shock
adt7490 rev. 0 | page 10 of 76 8 6 4 2 0 ?2 ?4 ?6 ?8 temperature error (c) series resistance ( ? ) 0 6789-071 0 200 400 600 800 1000 1200 1400 1600 dev 1 dev 2 dev 3 figure 10. temperature error vs. series resistance ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 100 200 300 400 500 600 temperature error (c) power supply noise frequency (mhz) 100mv 250mv 06789-011 figure 11. local temperature error vs. power supply noise frequency 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 temperature error (c) 100mv 250mv 0 100 200 300 400 500 600 power supply noise frequency (mhz) 0 6789-012 figure 12. remote temperature error vs. power supply noise frequency 20 15 10 5 0 ?5 ?10 temperature error (c) 0 100 200 300 400 500 600 common-mode noise frequency (mhz) 0 6789-013 100mv 40mv 60mv figure 13. temperature error vs. common-mode noise frequency 160 140 120 100 80 60 40 20 0 ?20 0 100 200 300 400 500 600 temperature error (c) differential mode noise frequency (mhz) 60mv 0 6789-014 40mv 100mv figure 14. temperature error vs. differential mode noise frequency 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 2 06 41 0 8 121416182022 temperature error (c) capacitance (nf) 0 6789-015 dev 3 dev 2 dev 1 figure 15. temperature error vs. capacitance between d+ and d?
adt7490 rev. 0 | page 11 of 76 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 accuracy (%) v dd (v) dev 2 06789-069 dev 3 dev 1 figure 16. tach accuracy vs. power supply 8 6 4 2 0 ?2 ?4 ?6 ?8 ?40 ?20 0 20 40 60 80 100 120 accuracy (%) temperature (c) 06789-070 dev 1 dev 3 dev 2 figure 17. tach accuracy vs. temperature
adt7490 rev. 0 | page 12 of 76 theory of operation the adt7490 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. the device communicates with the system via a serial system management bus. the serial bus controller has a serial data line for reading and writing addresses and data (pin 1), and an input line for the serial clock (pin 2). all control and programming functions for the adt7490 are performed over the serial bus. in addition, pin 14 can be reconfigured as an smbalert output to signal out-of-limit conditions. feature comparisons between the adt7490 and adt7476a the adt7490 is pin and register map compatible with the adt7476a. the new or additional features are detailed in the following sections. peci input cpu thermal information is provided through the peci input. the adt7490 has peci master capabilities and can read the cpu thermal information through the peci interface. each cpu address can have up to two peci domains. the adt7490 has the ability to record four peci temperature readings corresponding to the four peci addresses of 0x30 to 0x33. the hotter of the two domains at any given address is stored in the peci value registers. a peci reading is a negative value, in degrees celsius, which represents the offset from the thermal control circuit (t cc ) activation temperature. peci information is not converted to absolute temperature reading. peci informa- tion is in a 16-bit twos complement value; however, the adt7490 records the sign bit as well as the bits from 12:6 in the 16-bit peci payload. see the platform environment control interface (peci) specification from intel? for more details on the peci data format. the peci format is represented in table 6 . table 6. peci data format msb upper nibble msb lower nibble s x x x x x x x sign bit integer value (0c to 127c) there are associated high and low limits for each peci reading that can be programmed. the limit values take the same format as the peci reading. therefore, the programmed limits are not absolute temperatures but a relative offset in degrees celcius from the t cc activation temperature. an out-of-limit event is recorded as follows: ? high limit > comparison performed ? low limit comparison performed an out-of-limit event is recorded in the associated status register and can be used to assert the smbalert pin. temperature data replace mode the replace mode is configured by setting bit 4 of register 0x36. in this mode, the data in the existing remote 1 registers are replaced by peci0 data and vice versa. this is a legacy mode that allows the thermal data from cpu1 to be stored in the same registers as in the adt7476a. this reduces the software changes in systems transitioning from cpus with thermal diodes to cpus with a peci interface. see the peci temperature measurement section for more details. fan control using peci information the cpu thermal information from peci can be used in the existing automatic fan control algorithms. this temperature reading remains relative to t cc activation temperature and the associated afc control parameters are programmed in relative temperatures as opposed to absolute temperatures, and are in the same format as detailed in table 6 . peci min , t range , and t control are user defined. pwm = 100% pwm max pwm min peci min (t min ) pwm = 0% t range t control (t max ) peci = 0 t cc 06789-005 figure 18. overview of automatic fan speed control using peci thermal information dynamic tmin fan control mode the automatic fan speed control incorporates a feature called dynamic t min control. this intelligent fan control feature reduces the design effort requir ed to program the automatic fan speed control loop and improv es the system acoustics. v tt input the v tt voltage is monitored on pin 8. this voltage is also used as the reference voltage for the peci interface. the v tt voltage must be connected to the adt7490 in order for the peci interface to be operational. i mon monitoring the i mon input on pin 19 can be used to monitor the i mon output of the analog devices adp319x family of vr10/vr11 controllers. i mon is a voltage representation of the cpu current. using the i mon value and the measured v ccp value on pin 23, the cpu power consumption may be calculated. see the appropriate analog devices flex mode data sheet for calculations. the i mon information can be considered as an early indication of an increase in cpu temperature.
adt7490 rev. 0 | page 13 of 76 start-up operation at startup, the adt7490 turns the fans on to 100% pwm. this allows the most robust operation at turn-on. serial bus interface control of the adt7490 is carried out using the serial system management bus (smbus). the adt7490 is connected to this bus as a slave device, under the control of a master controller. the adt7490 has a 7-bit serial bu s address. when the device is powered up with pin 13 (pwm3/ addren ) high, the adt7490 has a default smbus address of 0101110 or 0x2e. the read/write bit must be added to get the 8-bit address. if more than one adt7490 is to be used in a system, each adt7490 is placed in address select mode by strapping pin 13 low on power-up. the logic state of pin 14 then determines the devices smbus address. the logic of these pins is sampled on power-up. the device address is sampled on power-up and latched on the first valid smbus transaction, more precisely on the low-to- high transition at the beginning of the eighth scl pulse, when the serial bus address byte matches the selected slave address. the selected slave address is chosen using the addren / addr select pins. any attempted changes in the address have no effect after this. table 7. hardwiring the adt7490 smbus device address pin 13 state pin 14 state address 0 low (10 k to gnd) 0101100 (0x2c) 0 high (10 k pull-up) 0101101 (0x2d) 1 dont care 0101110 (0x2e) data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as no acknowledge. the master takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. in the adt7490, write operations contain either one or two bytes, and read operations contain one byte. to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed. then data can be written into that register or read from it. the first byte of a write operation always contains an address that is stored in the address pointer register. if data is to be written to the device, the write operation must contain a second data byte that is written to the register selected by the address pointer register. this write operation is shown in figure 19 . the device address is sent over the bus, and then r/ w is set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. when reading data from a register, there are two possibilities: ? if the adt7490 address pointer register value is unknown or not the desired value, it must first be set to the correct value before data can be read from the desired data register. this is done by performing a write to the adt7490 as before, but only the data byte containing the register address is sent because no data is written to the register. this is shown in figure 20 . a read operation is then performed consisting of the serial bus address, r/ w bit set to 1, followed by the data byte read from the data register. this is shown in figure 21 . ? if the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in figure 21 .
adt7490 rev. 0 | page 14 of 76 r/w 0 scl s da 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7490 start by master 19 1 ack. by adt7490 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7490 stop by master 1 9 scl (continued) sda (continued) frame 1 serial bus address byte frame 2 addr ess pointer register byte frame 3 data byte 06789-016 figure 19. writing a register address to the address pointe r register, then writing data to the selected register r/w 0 scl sda 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7490 stop by master start by master frame 1 serial bus address byte frame 2 address pointer register byte 1 19 ack. by adt7490 9 06789-017 figure 20. writing to the address pointer register only r/w 0 scl sda 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 no ack. by master stop by master start by master frame 1 serial bus address byte frame 2 data byte from adt7490 1 19 ack. by adt7490 9 06789-018 figure 21. reading data from a previously selected register it is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value. however, it is not possi- ble to write data to a register without writing to the address pointer register because the first data byte of a write is always written to the address pointer register. in addition to supporting the send byte and receive byte protocols, the adt7490 also supports the read byte protocol (see system management bus specifications rev. 2 for more information; this document is available from the smbus organization). if several read or write operations must be performed in succes- sion, the master can send a repeat start condition instead of a stop condition to begin a new operation. write operations the smbus specification defines several protocols for different types of read and write operations. the ones used in the adt7490 are discussed here. the following abbreviations are used in the diagrams: ? s: start ? p: stop ? r: read ? w : write ? a: acknowledge ? a : no acknowledge the adt7490 uses the following smbus write protocols.
adt7490 rev. 0 | page 15 of 76 send byte in this operation, the master device sends a single command byte to a slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda and the transaction ends. for the adt7490, the send byte protocol is used to write a register address to ram for a subsequent single-byte read from the same address. this operation is illustrated in figure 22 . slave address wa sa register address 23 15 4 p 6 06789-019 figure 22. setting a register address for subsequent read if the master is required to read data from the register immedi- ately after setting up the address, it can assert a repeat start condition immediately after the final ack and carry out a single-byte read without asserting an intermediate stop condition. write byte in this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda, and the transaction ends. the byte write operation is illustrated in figure 23 . slave address wa data sa register address 23 15 4 a p 6 7 8 06789-020 figure 23. single byte write to a register read operations the adt7490 uses the following smbus read protocols. receive byte this operation is useful when repeatedly reading a single register. the register address must be previously set up. in this operation, the master device receives a single byte from a slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives a data byte. 5. the master asserts no ack on sda. 6. the master asserts a stop condition on sda, and the transaction ends. in the adt7490, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. this operation is illustrated in figure 24 . slave address data ar sa 24 3 15 p 6 06789-021 figure 24. single-byte read from a register alert response address alert response address (ara) is a feature of smbus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. the smbalert output can be used as either an interrupt output or an smbalert . one or more outputs can be connected to a common smbalert line connected to the master. if a devices smbalert line goes low, the following events occur: 1. smbalert is pulled low. 2. the master initiates a read operation and sends the alert response address (ara = 0001 100). this is a general call address that must not be used as a specific device address. 3. the device whose smbalert output is low responds to the alert response address, and the master reads its device address. the address of the device is now known and can be interrogated in the usual way. 4. if more than one devices smbalert output is low, the one with the lowest device address has priority in accor- dance with normal smbus arbitration. 5. once the adt7490 has responded to the alert response address, the master must read the status registers, and the smbalert is cleared only if the error condition is gone.
adt7490 rev. 0 | page 16 of 76 smbus timeout the adt7490 includes an smbus timeout feature. if there is no smbus activity for 35 ms, the adt7490 assumes the bus is locked and releases the bus. this prevents the device from locking or holding the smbus expecting data. some smbus controllers cannot work with the smbus timeout feature, so it can be disabled. configuration register 7 (register 0x11) bit 4 (todis) = 0, smbus timeout enabled (default). bit 4 (todis) = 1, smbus timeout disabled. voltage measurement input the adt7490 has six external voltage measurement channels. it can also measure its own supply voltage, v cc . pin 20 to pin 23 can measure 5 v, 12 v, and 2.5 v supplies, and the processor core voltage v ccp (0 v to 3 v input). the 2.5 v input can be used to monitor a chipset supply voltage in computer systems. the v cc supply voltage measurement is carried out through the v cc pin (pin 4). pin 8 measures the processors v tt voltage and is the dedicated reference voltage for the peci circuitry. the i mon input on pin 19 can be used to monitor the i mon output of the analog devices adp319x family of vr10/vr11 controllers. i mon is a voltage representation of the cpu current. analog-to-digital converter all analog inputs are multiplexed into the on-chip, successive- approximation, analog-to-digital converter. this adc has a resolution of 10 bits. the basic input range is 0 v to 2.25 v, but the inputs have built-in attenuators to allow measurement of 2.5 v, 3.3 v, 5 v, 12 v, and the processor core voltage v ccp without any external components. to allow the tolerance of these supply voltages, the adc produces an output of ? full scale (768 dec or 0x300 hex) for the nominal input voltage, and therefore, has adequate headroom to cope with overvoltages. input circuitry the internal structure for the analog inputs is shown in figure 25 . the input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order low-pass filter that gives input immunity to high frequency noise. voltage measurement registers register 0x1d, i mon reading = 0x00 default register 0x1e, v tt reading = 0x00 default register 0x20, +2.5v in reading = 0x00 default register 0x21, v ccp reading = 0x00 default register 0x22, v cc reading = 0x00 default register 0x23, +5v in reading = 0x00 default register 0x24, +12v in reading = 0x00 default v tt 45k? 45k? 30pf i mon 45k? 94k? 30pf v ccp 17.5k ? 52.5k ? 35pf 2.5v in 45k? 94k? 30pf 3.3v in 68k? 71k? 30pf 5v in 93k? 47k? 30pf 12v in 120k ? 20k? 30pf mux 06789-025 figure 25. analog inputs structure voltage limit registers associated with each voltage measurement channel is a high and low limit register. exceeding the programmed high or low limit causes the appropriate status bit to be set. exceeding either limit can also generate smbalert interrupts. register 0x85, i mon low limit = 0x00 default register 0x87, i mon high limit = 0xff default register 0x84, v tt low limit = 0x00 default register 0x86, v tt high limit = 0xff default register 0x44, +2.5v in low limit = 0x00 default register 0x45, +2.5v in high limit = 0xff default register 0x46, v ccp low limit = 0x00 default register 0x47, v ccp high limit = 0xff default register 0x48, v cc low limit = 0x00 default register 0x49, v cc high limit = 0xff default register 0x4a, +5v in low limit = 0x00 default register 0x4b, +5v in high limit = 0xff default register 0x4c, +12v in low limit = 0x00 default register 0x4d, +12v in high limit = 0xff default when the adc is running, it samples and converts a voltage input in 0.7 ms and averages 16 conversions to reduce noise; a measurement takes nominally 11 ms.
adt7490 rev. 0 | page 17 of 76 extended resolution registers voltage measurements can be made with higher accuracy using the extended resolution registers (0x1f, 0x76, and 0x77). whenever the extended resolution registers are read, the corresponding data in the voltage measurement registers (0x1d, 0x1e, and 0x20 to 0x24) is locked until their data is read. that is, if extended resolution is required, the extended resolution register must be read first, imme diately followed by the appropriate voltage measurement register. additional adc functions for voltage measurements a number of other functions are available on the adt7490 to offer the system designer increased flexibility. the functions described in the following sections are enabled by setting the appropriate bit in configuration register 2. configuration register 2 (register 0x73) bit 4 (avg) = 1, averaging off. bit 5 (attn) = 1, bypass input attenuators. bit 6 (conv) = 1, single-channel convert mode. turn-off averaging for each voltage/temperature measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value reg- ister. when faster conversions are needed, setting bit 4 (avg) of configuration register 2 (0x73) turns averaging off. this effectively gives a reading that is 16 times faster, but the reading can be noisier. the default round-robin cycle time takes 146.5 ms. table 8. conversion time with averaging disabled channel measurement time (ms) voltage channels 0.7 remote temperature 1 7 remote temperature 2 7 local temperature 1.3 when bit 7 (extraslow) of configuration register 6 (0x10) is set, the default round-robin cycle time increases to 240 ms. bypass all voltage input attenuators setting bit 5 of configuration register 2 (register 0x73) removes the attenuation circuitry from the 2.5 v in , v ccp , v cc , 5 v in , and 12 v in inputs. this allows the user to directly connect external sensors or rescale the analog voltage measure- ment inputs for other applications. the input range of the adc without the attenuators is 0 v to 2.25 v. bypass individual voltage input attenuators bits [7:4] of configuration register 4 (0x7d) can be used to bypass individual voltage channel attenuators. table 9. bypassing individual voltage input attenuators configuration register 4 (0x7d) bit no. channel attenuated 4 bypass +2.5v in attenuator 5 bypass v ccp attenuator 6 bypass +5v in attenuator 7 bypass +12v in attenuator single-channel adc conversion while single-channel mode is intended as a test mode that can be used to increase sampling times for a specific channel, therefore helping to analyze that channels performance in greater detail, it can also have other applications. setting bit 6 of configuration register 2 (0x73) places the adt7490 into single-channel adc conversion mode. in this mode, the adt7490 can read a single voltage channel only. the selected voltage input is read every 0.7 ms. the appropriate adc channel is selected by writing to bits [7:4] of the tach1 minimum high byte register (0x55). table 10. programming single-channel adc mode bits [7:4] register 0x55 channel selected 1 0000 +2.5v in 0001 v ccp 0010 v cc 0011 +5v in 0100 +12v in 0101 remote 1 temperature 0110 local temperature 0111 remote 2 temperature 1000 v tt 1001 i mon 1 in the process of conf iguring single-channel adc conversion mode, the tach1 minimum high byte is also changed, possibly trading off tach1 minimum high byte functionality with single-channel mode functionality.
adt7490 rev. 0 | page 18 of 76 table 11. 10-bit adc output code vs. v in input voltage adc output +12v in +5v in v cc (3.3 v in ) +2.5v in v ccp v tt /i mon decimal binary (10 bits) <0.0156 <0.0065 <0.0042 <0.0032 <0.00293 <0.00220 0 00000000 00 0.0156 to 0.0312 0.0065 to 0.0130 0.0042 to 0.0085 0.0032 to 0.0065 0.0293 to 0.0058 0.00220 to 0.00440 1 00000000 01 0.0312 to 0.0469 0.0130 to 0.0195 0.0085 to 0.0128 0.0065 to 0.0097 0.0058 to 0.0087 0.00440 to 0,00660 2 00000000 10 0.0469 to 0.0625 0.0195 to 0.0260 0.0128 to 0.0171 0.0097 to 0.0130 0.0087 to 0.0117 0,00660 to 0.00881 3 00000000 11 0.0625 to 0.0781 0.0260 to 0.0325 0.0171 to 0.0214 0.0130 to 0.0162 0.0117 to 0.0146 0.00881 to 0.01100 4 00000001 00 0.0781 to 0.0937 0.0325 to 0.0390 0.0214 to 0.0257 0.0162 to 0.0195 0.0146 to 0.0175 0.01100 to 0.01320 5 00000001 01 0.0937 to 0.1093 0.0390 to 0.0455 0.0257 to 0.0300 0.0195 to 0.0227 0.0175 to 0.0205 0.01320 to 0.01541 6 00000001 10 0.1093 to 0.1250 0.0455 to 0.0521 0.0300 to 0.0343 0.0227 to 0.0260 0.0205 to 0.0234 0.01541 to 0.01761 7 00000001 11 0.1250 to 0.14060 0.0521 to 0.0586 0.0343 to 0.0386 0.0260 to 0.0292 0.0234 to 0.0263 0.01761 to 0.01981 8 00000010 00 4.0000 to 4.0156 1.6675 to 1.6740 1.1000 to 1.1042 0.8325 to 0.8357 0.7500 to 0.7529 0.5636 to 0.5658 256 (? scale) 01000000 00 8.0000 to 8.0156 3.3300 to 3.3415 2.2000C2.2042 1.6650 to 1.6682 1.5000 to 1.5029 1.1272 to 1.1294 512 (? scale) 10000000 00 12.0000 to 12.0156 5.0025 to 5.0090 3.3000C3.3042 2.4975 to 2.5007 2.2500 to 2.2529 1.6809 to 1.6930 768 (? scale) 11000000 00 15.8281 to 15.8437 6.5983 to 6.6048 4.3527 to 4.3570 3.2942 to 3.2974 2.9677 to 2.9707 2.2301 to 2.2323 1013 11111101 01 15.8437 to 15.8593 6.6048 to 6.6113 4.3570 to 4.3613 3.2974 to 3.3007 2.9707 to 2.9736 2.2323 to 2.2346 1014 11111101 10 15.8593 to 15.8750 6.6113 to 6.6178 4.3613 to 4.3656 3.3007 to 3.3039 2.9736 to 2.9765 2.2346 to 2.2368 1015 11111101 11 15.8750 to 15.8906 6.6178 to 6.6244 4.3656 to 4.3699 3.3039 to 3.3072 2.9765 to 2.9794 2.2368 to 2.23899 1016 11111110 00 15.8906 to 15.9062 6.6244 to 6.6309 4.3699 to 4.3742 3.3072 to 3.3104 2.9794 to 2.9824 2,23899 to 2.2412 1017 11111110 01 15.9062 to 15.9218 6.6309 to 6.6374 4.3742 to 4.3785 3.3104 to 3.3137 2.9824 to 2.9853 2.2412 to 2.2434 1018 11111110 10 15.9218 to 15.9375 6.6374 to 6.4390 4.3785 to 4.3828 3.3137 to 3.3169 2.9853 to 2.9882 2.2434 to 2.2456 1019 11111110 11 15.9375 to 15.9531 6.6439 to 6.6504 4.3828 to 4.3871 3.3169 to 3.3202 2.9882 to 2.9912 2.2456 to 2.2478 1020 11111111 00 15.9531 to 15.9687 6.6504 to 6.6569 4.3871 to 4.3914 3.3202 to 3.3234 2.9912 to 2.9941 2.2478 to 2.25 1021 11111111 01 15.9687 to 15.9843 6.6569 to 6.6634 4.3914 to 4.3957 3.3234 to 3.3267 2.9941 to 2.9970 2.25 to 2.2522 1022 11111111 10 >15.9843 >6.6634 >4.3957 >3.3267 >2.9970 >2.2522 1023 11111111 11
adt7490 rev. 0 | page 19 of 76 temperature measurement the adt7490 has four temperature measurement channels: one local, two remote thermal diodes, and a peci. the local and thermal diode readings are analog temperature measure- ments, whereas peci is a digital temperature reading. peci temperature measurement the peci interface is a dedicated thermal interface. the cpu temperature measurement is carried out internally in the cpu. this information is digitized and transferred to the adt7490 via the peci interface. the adt7490 is a peci host device and therefore, polls the cpu for thermal information. the peci measurement differs from traditional thermal diode temperature measurements in that the measurement is a relative value instead of an absolute value. the peci reading is a nega- tive value that indicates how close the cpu temperature is from the thermal throttling or t cc point of the cpu. the adt7490 records and uses the peci measurement for fan control in its relative format. therefore, care must be taken in programming the relevant limits and fan control parameters in the peci format. refer to the peci input section and table 6 for further peci information. peci monitoring is enabled on the adt7490 by setting the peci monitoring bit in configuration register 1 (register 0x40, bit 4). the adt7490 can measure the temperature of up to four dual-core cpus. the number of cpus in the system that provide peci information is set in bits [7:6] of register 0x88. each cpu is distinguished by the peci address. the number of domains, or domain count, per cpu address must also be programmed into the adt749 0. the adt7490 reads the temperature of both domains per cpu, however, only the peci value of the hottest domain is recorded in the peci value register. peci0 domains: register 0x36, bit 3 peci1 domains: register 0x88, bit 5 peci2 domains: register 0x88, bit 4 peci3 domains: register 0x88, bit 3 peci reading registers register 0x33, peci0: peci reading from cpu address 0x30 register 0x1a, peci1: peci reading from cpu address 0x31 register 0x1b, peci2: peci reading from cpu address 0x32 register 0x1c, peci3: peci reading from cpu address 0x33 peci limit registers each peci measurement shares the same high and low limits. register 0x34, peci low limit = 0x81 default register 0x35, peci high limit = 0x00 default peci offset registers each peci reading has a dedicated offset register to calibrate the peci measurement and account for errors in the tempera- ture reading. the lsbs add a 1c offset to the temperature reading so that the 8-bit register effectively allows temperature offsets of up to 128c with a resolution of 1c. register 0x94, peci0 offset register 0x95, peci1 offset register 0x96, peci2 offset register 0x97, peci3 offset peci data smoothing the peci smoothing interval is programmed in peci configuration register 1 (0x36). bits [2:0] of register 0x36 set the duration over which the peci data being read by the adt7490 is averaged. these bits set the duration over which smoothing is carried out on the peci data read. the refresh rate in the peci value registers is the same as the smoothing interval programmed. the smoothing interval is calculated using the following formula: ) #67(# idle bit tcpu treads interval smoothing + = where: #reads is the number of readings defined in register 0x36, bits [2:0]. t bit is the negotiated bit rate. 67 is the number of bits in each peci reading. #cpu is the number of cpus providing peci data (1 to 4). t idle = 14 s, the delay between consecutive reads. for example, #reads = 4096 t bit = 1 s (1 mhz speed) #cpu = 1 smoothing interval = 331 ms = peci reading refresh rate. peci error codes there are two different error conditions for peci data, peci data errors, and peci bus communications errors. tabl e 12 describes the two different error conditions. if the adt7490 reads an error code (0x8000 to 0x8003) from the cpu over the peci interface, bit 1 is set in interrupt status 3 register (0x43), indicating a data error. the value of the error code is not included in the peci value averaging sum. this means that a value of 0x00 is added to the peci sum when an error code is recorded. the error code is not reported in the appropriate peci value register. if an invalid fcs is recorded by the adt7490, bit 2 is set in the interrupt status 3 register (0x43), indicating a communications error. an alert is generated on the smbalert pin when either or both of these status bits are asserted.
adt7490 rev. 0 | page 20 of 76 table 12. peci error indicators peci data description action 0x8000 to 0x8003 peci data error bit 1 of register 0x43 is set to 1 invalid fcs peci communications error bit 2 of register 0x43 is set to 1 each peci channel also has an associated status bit to indicate if the peci high or low limits have been exceeded. an alert is generated on the smbalert pin when these status bits are asserted. table 13. peci status bits channel register bit peci0 0x43 0 peci1 0x81 3 peci2 0x81 4 peci3 0x81 5 temperature data replace mode the replace mode is configured by setting bit 4 of register 0x36. in this mode, the data in the existing remote 1 registers are replaced by peci0 data. this is a legacy mode that allows the thermal data from cpu1 to be stored in the same registers as in the adt7476a. this reduces the software changes in systems transitioning from cpus with thermal diodes to cpus with a peci interface. however, note that even though the associated registers are swapped, the correct data format (peci vs. absolute temperature, see table 6 ) must be written to and interpreted from these registers. notes in table 14 , registers listed under the remote 1 default column are in absolute temperature format by default and are in peci format in replace mode. registers listed under the peci0 default column are in peci format by default and in absolute temperature format in replace mode. table 14. replace mode temperature registers register name remote 1 default peci0 default value register reg. 0x25 reg. 0x33 low limit reg. 0x4e reg. 0x34 high limit reg. 0x4f reg. 0x35 t min reg. 0x67 reg. 0x3b t range reg. 0x5f, bits [7:4] reg. 0x3c, bits [7:4] enhanced acoustics reg. 0x62, bits [2:0] reg. 0x3c, bits [2:0] enhanced acoustics enable reg. 0x62, bit 3 reg. 0x3c, bit 3 therm t control reg. 0x6a reg. 0x3d reg. 0x6d, bits [7:4] reg. 0x6e, bits [3:0] t min hysteresis reg. 0x6d, bits [3:0] 1 reg. 0x6e, bits [7:4] 1 temperature offset reg. 0x70 reg. 0x94 operating point for dynamic t min reg. 0x8b reg. 0x8a 1 in replace mode, the remote 2 and local temperature hysteresis values are swapped. in replace mode, the temperature zone controlling the relevant pwm output are also swapped from remote 1 to peci0. the swap of control only occurs if the default behavior setting for register 0x5c bits [7:5], register 0x5d bits [7:5] or register 0x5e bits [7:5] is 000. local temperature measurement the adt7490 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip 10-bit adc. the 8-bit msb temperature data is stored in the local tempera- ture register (address 0x26). because both positive and negative temperatures can be measured, the temperature data is stored in offset 64 format or twos complement format, as shown in table 15 and table 16 . theoretically, the temperature sensor and adc can measure temperatures from ?63c to +127c (or ?63c to +191c in the extended temperature range) with a resolution of 0.25c. however, this exceeds the operating temperature range of the device, so local temperature measurements outside the adt7490 operating temperature range are not possible. table 15. twos complement temperature data format temperature digital output (10-bit) 1 C128c 1000 0000 00 (diode fault) C63c 1100 0001 00 C50c 1100 1110 00 C25c 1110 0111 00 C10c 1111 0110 00 0c 0000 0000 00 10.25c 0000 1010 01 25.5c 0001 1001 10 50.75c 0011 0010 11 75c 0100 1011 00 100c 0110 0100 00 125c 0111 1101 00 127c 0111 1111 00 1 bold numbers denote 2 lsbs of measurement in the extended resolution 2 register (register 0x77) with 0.25c resolution. table 16. offset 64 data format temperature digital output (10-bit) 1 C64c 0000 0000 00 (diode fault) C63c 0000 0001 00 C1c 0011 1111 00 0c 0100 0000 00 1c 0100 0001 00 10c 0100 1010 00 25c 0101 1001 00 50c 0111 0010 00 75c 1000 1001 00 100c 1010 0100 00 125c 1011 1101 00 191c 1111 1111 00 1 bold numbers denote 2 lsbs of measurement in the extended resolution 2 register (register 0x77) with 0.25c resolution.
adt7490 rev. 0 | page 21 of 76 remote temperature measurement thermal diode temperature measurement method the adt7490 can measure the temperature of two remote diode sensors or diode-connected transistors connected to pin 10 and pin 11, or pin 12 and pin 13. a simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the base- emitter voltage (v be ) of a transistor operated at constant current. unfortunately, this technique requires calibration to null out the effect of the absolute value of v be , which varies from device to device. the forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about ?2 mv/c. unfortunately, the absolute value of v be varies from device to device, and individual calibration is required to null this out. therefore, the technique is unsuitable for mass production. the technique used in the adt7490 is to measure the change in v be when the device is operated at three different currents. this is given by the technique used in the adt7490 is to measure the change in v be when the device is operated at three different currents. previous devices have used only two operating currents, but the use of a third current allows automatic cancellation of resis- tances in series with the external temperature sensor. )ln( n q kt v be = figure 29 shows the input signal conditioning used to measure the output of an external temperature sensor. this figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor, such as a 2n3904/2n3906. where: k is the boltzmann constant. q is the charge on the carrier. t is the absolute temperature in kelvin. n is the ratio of the two currents. if a discrete transistor is used, the collector is not grounded and should be linked to the base. if a pnp transistor is used, the base is connected to the dC input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the dC input and the base to the d+ input. figure 26 and figure 27 show how to connect the adt7490 to an npn or pnp transis- tor for temperature measurement. to me asure v be , the operating current through the sensor is switched among three related currents. n1 i and n2 i are different multiples of the current i, as shown in figure 28 . the currents through the temperature diode are switched between i and n1 i, giving v be1 , and then between i and n2 i, giving v be2 . the temperature can then be calculated using the two v be measurements. this method can also cancel the effect of any series resistance on the temperature measurement. 2 n3904 npn adt7490 d+ d? 06789-027 the resulting v be waveforms are passed through a 65 khz low-pass filter to remove noise and then to a chopper-stabilized amplifier. this amplifies and rectifies the waveform to produce a dc voltage proportional to v be . the adc digitizes this voltage, and a temperature measurement is produced. to reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. figure 26. measuring temperature using an npn transistor 2 n3906 pnp adt7490 d+ d? 06789-028 the results of remote temperature measurements are stored in 10-bit, twos complement format, as listed in table 15 . the extra resolution for the temperature measurements is held in the extended resolution register 2 (0x77). this gives temperature readings with a resolution of 0.25c. figure 27. measuring temperature using a pnp transistor to prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the d? input. c1 can optionally be added as a noise filter (recommended maximum value of 1000 pf). however, a better option in noisy environments is to add a filter, as described in the series resistance cancellation section.
adt7490 rev. 0 | page 22 of 76 d+ v dd to adc v out+ v out? remote sensing transistor d? i n1 i n2 i i bias lpf f c = 65khz 06789-023 figure 28. signal conditioning for remote diode temperature sensors series resistance cancellation parasitic resistance to the adt7490 d+ and d? inputs (seen in series with the remote diode) is caused by a variety of factors, including pcb track resistance and track length. this series resistance appears as a temperature offset in the remote sensors temperature measurement. this error typically causes a 0.5c offset per ohm of parasitic resistance in series with the remote diode. the adt7490 automatically cancels out the effect of this series resistance on the temperature reading, giving a more accurate result without the need for user characterization of this resis- tance. the adt7490 is designed to automatically cancel, typically up to 1.5 k of resistance. by using an advanced temperature measurement method, this is transparent to the user. this feature allows resistances to be added to the sensor path to produce a filter, allowing the part to be used in noisy environments. noise filtering for temperature sensors operating in noisy environments, previous practice was to place a capacitor across the d+ pin and the d? pin to help combat the effects of noise. however, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pf. this capacitor reduces the noise, but does not eliminate it, which makes using the sensor difficult in a very noisy environment. the adt7490 has a major advantage over other devices for eliminating the effects of noise on the external sensor. using the series resistance cancellation feature, a filter can be constructed between the external temperature sensor and the part. the effect of any filter resistance seen in series with the remote sensor is automatically canceled from the temperature result. the construction of a filter allows the adt7490 and the remote temperature sensor to operate in noisy environments. figure 29 shows a low-pass rc filter with the following values: r = 100 , c = 1 nf this filtering reduces both common-mode noise and differential noise. d+ 1nf 100 ? remote temperature sensor d? 100 ? 06789-024 figure 29. filter between remote sensor and adt7490 factors affecting diode accuracy remote sensing diode the adt7490 is designed to work with either substrate transistors built into processors or discrete transistors. substrate transistors are generally pnp types with the collector connected to the substrate. discrete types can be either pnp or npn transistors connected as a diode (base-shorted to the collector). to reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration: x the ideality factor, n f , of the transistor is a measure of the deviation of the thermal diode from ideal behavior. the adt7490 is trimmed for an n f value of 1.008. use the following equation to calculate the error introduced at a temperature t (c) when using a transistor whose n f does not equal 1.008. refer to the data sheet for the related cpu to obtain the n f values. t = ( n f ? 1.008)/1.008 (273.15 k + t ) to factor this in, the user can write the t value to the offset register. the adt7490 automatically adds it to or subtracts it from the temperature measurement. x some cpu manufacturers specify the high and low current levels of the substrate transistors. the high current level of the adt7490, i high , is 192 a and the low level current, i low , is 12 a. if the adt7490 current levels do not match the current levels specified by the cpu manufacturer, it may be necessary to remove an offset. the cpus data sheet advises whether this offset needs to be removed and how to calculate it. this offset can be programmed to the offset register. it is important to note that if more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register.
adt7490 rev. 0 | page 23 of 76 if a discrete transistor is used with the adt7490, the best accuracy is obtained by choosing devices according to the following criteria: ? base-emitter voltage greater than 0.25 v at 12 a at the highest operating temperature. ? base-emitter voltage less than 0.95 v at 192 a at the lowest operating temperature. ? base resistance less than 100 . ? small variation in h fe (such as 50 to 150) that indicates tight control of v be characteristics. transistors, such as 2n3904, 2n3906, or equivalents in sot-23 packages, are suitable devices to use. reading temperature from the adt7490 it is important to note that temperature can be read from the adt7490 as an 8-bit value (with 1c resolution) or as a 10-bit value (with 0.25c resolution). if only 1c resolution is re- quired, the temperature readings can be read back at any time and in no particular order. if the 10-bit measurement is required, it involves a 2-register read for each measurement. the extended resolution 2 register (0x77) should be read first. this causes all temperature reading registers to be frozen until all temperature reading registers have been read from. this prevents an msb reading from being updated while its two lsbs are being read and vice versa. nulling out temperature errors as cpus run faster, it becomes more difficult to avoid high frequency clocks when routing the d+/d? traces around a system board. even when recommended layout guidelines are followed, some temperature errors may still be attributable to noise coupled onto the d+/d? lines. constant high frequency noise usually attenuates or increases temperature measurements by a linear, constant value. the adt7490 has temperature offset registers at address 0x70, address 0x71, and address 0x72 for the remote 1, local, and remote 2 temperature channels, respectively. by performing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it out using the offset registers. the offset registers automatically add a twos complement 8-bit reading to every temperature measurement. the temperature offset range and resolution is selected by setting bit 1 of register 0x7c. this ensures that the readings in the temperature measurement registers are as accurate as possible. setting this bit to 0 means the lsbs add 0.5c offset to the temperature reading, so the 8-bit register effectively allows temperature offsets from ?63c to +64c with a resolu- tion of 0.5c. setting this bit to 1 means the lsbs add 1c offset to the temperature reading, so the 8-bit register effectively allows temperature offsets of up to ?63c to +127c with a resolution of 1c. for the peci offset registers, the resolution is always 1c. temperature offset registers register 0x70, remote 1 temperature offset = 0x00 (0c default) register 0x71, local temperature offset = 0x00 (0c default) register 0x72, remote 2 temperature offset = 0x00 (0c default) register 0x94, peci0 temperature offset = 0x00 (0c default) register 0x95, peci1 temperature offset = 0x00 (0c default) register 0x96, peci2 temperature offset = 0x00 (0c default) register 0x97, peci3 temperature offset = 0x00 (0c default) temperature measurement limit registers associated with each temperature measurement channel are high and low limit registers. exceeding the programmed high or low limit causes the appropriate status bit to be set. exceeding either limit can also generate smbalert interrupts (depend- ing on the way the interrupt mask register is programmed and assuming that smbalert is set as an output on the appropriate pin). additional adc functions for temperature measurement a number of other functions are available on the adt7490 to offer the system designer increased flexibility. turn-off averaging for each temperature measurement read from a value register, 16 readings have actually been made internally, and the results averaged, before being placed into the value register. sometimes it is necessary to take a very fast measurement. setting bit 4 of configuration register 2 (0x73) turns averaging off. the default round-robin cycle time with averaging off is a maximum of 23 ms. table 17. conversion time with averaging disabled channel measurement time (ms) voltage channels 0.7 remote temperature 1 7 remote temperature 2 7 local temperature 1.3 when bit 7 of configuration register 6 (0x10) is set, the default round-robin cycle time increases to a maximum of 193 ms. table 18. conversion time with averaging enabled channel measurement time (ms) voltage channels 11 remote temperature 39 local temperature 12
adt7490 rev. 0 | page 24 of 76 single-channel adc conversions the fans run at this speed until the temperature drops below therm minus hysteresis. this can be disabled by setting the boost bit in configuration register 3, bit 2 (0x78). the hysteresis value for the therm temperature limit is the value programmed into the hysteresis registers (0x6d and 0x6e). the default hysteresis value is 4c. setting bit 6 of configuration register 2 (register 0x73) places the adt7490 into single-channel adc conversion mode. in this mode, the adt7490 can be made to read a single temperature channel only. the appropriate adc channel is selected by writing to bits [7:4] of the tach1 minimum high byte register (0x55). table 19. programming single-channel adc mode for temperatures bits [7:4], register 0x55 channel selected 0101 remote 1 temperature 0110 local temperature 0111 remote 2 temperature fans temperature 100% hysteresis (c) therm limit 06789-029 configuration register 2 (register 0x73) figure 30. therm temperature limit operation bit 4 (avg) = 1, averaging off. therm can be disabled by setting bit 2 of configuration register 4 (0x7d). therm can also be disabled by: bit 6 (conv) = 1, single-channel convert mode. overtemperature events ? in offset 64 mode, writing ?64c to the appropriate therm temperature limit. overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. register 0x6a to register 0x6c are the therm temperature limits for the local and remote diode temperature channels. the equivalent peci limit is t control in register 0x3d. when a temperature exceeds its therm temperature limit, all pwm outputs run at 100% duty cycle (default). this can be changed to maximum pwm duty cycle as programmed in register 0x38, register 0x39, and register 0x3a, by setting bit 3 of register 0x7d. ? in twos complement mode , writing ?128c to the appropriate therm temperature limit.
adt7490 rev. 0 | page 25 of 76 limits, status registers, and interrupts limit values associated with each measurement channel on the adt7490 are high and low limits. these can form the basis of system status monitoring; a status bit can be set for any out-of-limit condition and is detected by polling the device. alternatively, smbalert interrupts can be generated to flag out-of-limit conditions to a processor or microcontroller. 8-bit limits the following is a list of 8-bit limits on the adt7490. voltage l imit re gisters register 0x44, +2.5v in low limit = 0x00 default register 0x45, +2.5v in high limit = 0xff default register 0x46, v ccp low limit = 0x00 default register 0x47, v ccp high limit = 0xff default register 0x48, v cc low limit = 0x00 default register 0x49, v cc high limit = 0xff default register 0x4a, +5v in low limit = 0x00 default register 0x4b, +5v in high limit = 0xff default register 0x4c, +12v in low limit = 0x00 default register 0x4d, +12v in high limit = 0xff default register 0x84, v tt low limit = 0x00 default register 0x86, v tt high limit = 0xff default register 0x85, i mon low limit = 0x00 default register 0x87, i mon high = 0xff default temperature limit registers register 0x4e, remote 1 temperature low limit = 0x81 default register 0x4f, remote 1 temperature high limit = 0x7f default register 0x6a, remote 1 therm limit = 0x64 default register 0x50, local temperature low limit = 0x81 default register 0x51, local temperature high limit = 0x7f default register 0x6b, local therm limit = 0x64 default register 0x52, remote 2 temperature low limit = 0x81 default register 0x53, remote 2 temperature high limit = 0x7f default register 0x6c, remote 2 therm limit = 0x64 default register 0x34, peci low limit = 0x81 default register 0x35, peci high limit = 0x00 default register 0x3d, peci t control limit = 0x00 default therm timer limit register register 0x7a, therm timer limit = 0x00 default 16-bit limits the fan tach measurements are 16-bit results. the fan tach limits are also 16 bits, consisting of a high byte and low byte. only high limits exist for fan tachs because fans running under speed or stalled are normally the only conditions of interest. because the fan tach period is actually being measured, exceeding the limit indicates a slow or stalled fan. fan limit registers register 0x54, tach1 minimum low byte = 0xff default register 0x55, tach1 minimum high byte = 0xff default register 0x56, tach2 minimum low byte = 0xff default register 0x57, tach2 minimum high byte = 0xff default register 0x58, tach3 minimum low byte = 0xff default register 0x59, tach3 minimum high byte = 0xff default register 0x5a, tach4 minimum low byte = 0xff default register 0x5b, tach4 minimum high byte = 0xff default out-of-limit comparisons once all limits have been programmed, the adt7490 can be enabled for monitoring. the adt7490 measures all voltage and temperature measurements in round-robin format and sets the appropriate status bit to indicate out-of-limit conditions. tach measurements are not part of this round-robin cycle. compari- sons are done differently depending on whether the measured value is being compared to a high or low limit. high limit > comparison performed low limit comparison performed voltage and temperature channels use a window comparator for error detecting and, therefore, have high and low limits. fan speed measurements use only a low limit. analog monitoring cycle time the analog monitoring cycle begins when a 1 is written to the start bit (bit 0) of configuration register 1 (0x40). the adc measures each analog input in turn, and, as each measurement is completed, the result is automatically stored in the appropriate value register. this round-robin monitoring cycle continues unless disabled by writing a 0 to bit 0 of configuration register 1. as the adc is normally left to free-run in this manner, the time taken to monitor all the analog inputs is normally not of interest, because the most recently measured value of any input can be read out at any time. for applications where the monitoring cycle time is important, it can easily be calculated.
adt7490 rev. 0 | page 26 of 76 the total number of channels measured consists of ? six dedicated supply voltage inputs ? supply voltage (v cc pin) ? local temperature ? two remote temperatures as mentioned previously, the adc performs round-robin conversions and takes 11 ms fo r each voltage measurement, 12 ms for a local temperature reading, and 39 ms for each remote temperature reading. th e total monitoring cycle time for averaged voltage and temperat ure monitoring is, therefore, nominally (7 11) + 12 + (2 39) = 167 ms fan tach measurements and peci thermal measurements are made in parallel and are not synchronized with the analog measurements in any way. interrupt status registers the results of limit comparisons are stored in interrupt status register 1 to interrupt status register 4. the status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. if a measurement is within limits, the corresponding interrupt status register bit is cleared to 0. if the measurement is out of limit, the corresponding interrupt status register bit is set to 1. the state of the various measurement channels can be polled by reading the interrupt status registers over the serial bus. in bit 7 (ool) of interrupt status register 1 (0x41), a logic 1 indicates an out-of-limit event has been flagged in interrupt status register 2. this means the user also needs to read interrupt status register 2. there is a similar ool bit in interrupt status register 2 and interrupt status register 3,indicating an out-of- limit event in the next status register. alternatively, pin 10 or pin 14 can be configured as an smbalert output. this hard interrupt automatically notifies the system supervisor of an out-of-limit condition. reading the interrupt status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. interrupt status register bits are sticky. whenever an interrupt status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it has gone away (until read). the only way to clear the interrupt status bit is to read the interrupt status register after the event has gone away. interrupt status mask registers allow indi vidual interrupt sources to be masked from causing an smbalert on the dedicated alert pin. however, if one of these masked interrupt sources goes out of limit, its associated interrupt status bit is set in the interrupt status registers. full details of the interrupt status and interrupt mask registers associated with each measurement channels are detailed in the table 20 and in the full register map in the register tables section. table 20. interrupt status and interrupt mask register address and bit assignments interrupt status register interrupt mask register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x41 0x74 ool r2t lt r1t +5v in v cc v ccp +2.5v in /therm 0x42 0x75 d2 fault d1 fault fan4/therm fan3 fan2 fan1 ool +12v in 0x43 0x82 ool res res res ovt comm data peci0 0x81 0x83 v tt i mon peci3 peci2 peci1 res res res
adt7490 rev. 0 | page 27 of 76 smbalert interrupt behavior the adt7490 can be polled for status, or an smbalert interrupt can be generated for out-of-limit conditions. it is important to note how the smbalert output and status bits behave when writing interrupt handler software. sticky status bit high limit temperature cleared on read (temp below limit) temp back in limit (status bit stays set) smbalert 0 6789-030 figure 31. smbalert and status bit behavior figure 31 shows how the smbalert output and sticky status bits behave. once a limit is exceeded, the corresponding status bit is set to 1. the status bit remains set until the error condi- tion subsides and the status register is read. the status bits are referred to as sticky , because they remain set until read by software. this ensures that an out-of-limit event cannot be missed if software is polling the device periodically. note that the smbalert output remains low for the entire duration that a reading is out of limit and until the status register has been read. this has implications on how soft- ware handles the interrupt. handling smbalert interrupts to prevent the system from being tied up servicing interrupts, it is recommend to handle the smbalert interrupt as follows: 1. detect the smbalert assertion. 2. enter the interrupt handler. 3. read the status registers to identify the interrupt source. 4. mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (0x74, 0x75, 0x82, and 0x83). 5. take the appropriate action for a given interrupt source. 6. exit the interrupt handler. 7. periodically poll the status registers. if the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. this causes the smbalert output and status bits to behave as shown in figure 32 . masking interrupt sources the interrupt mask registers allow individual interrupt sources to be masked out to prevent smbalert interrupts. note that masking an interrupt source prevents only the smbalert output from being asserted; the appropriate status bit is set normally see figure 32 . full details of the status and mask registers associated with each measurement channel are detailed in tabl e 20 and tabl e 2 4 . sticky status bit high limit temperature cleared on read (temp below limit) temp back in limit (status bit stays set) interrupt mask bit set smbalert interrupt mask bit cleared (smbalert rearmed) 06789-031 figure 32. how masking the interrupt source affects smbalert output enabling the smbalert interrupt output the smbalert interrupt function is disabled by default. pin 10 or pin 14 can be reconfigured as an smbalert output to signal out-of-limit conditions. table 21. configuring pin 10 as smbalert output register bit setting configuration register 3 (register 0x78) bit 0 [1] pin 10 = smbalert [0] pin 10 = pwm2 (default) assigning therm functionality to a pin pin 14 on the adt7490 has three possible functions: smbalert , therm , and tach4. the user chooses the required functionality by setting bit 0 and bit 1 of configuration register 4 at address 0x7d. if therm is enabled (bit 1, configuration register 3 at address 0x78): ? pin 22 becomes therm . ? if pin 14 is configured as therm (bit 0 and bit 1 of configuration register 4 at address 0x7d), therm is enabled on this pin. if therm is not enabled: ? pin 22 becomes a 2.5 v in measurement input. ? if pin 14 is configured as therm , therm is disabled on this pin. table 22. configuring pin 14 in register 0x7d bit 0 bit 1 function 0 0 tach4 0 1 therm 1 0 smbalert 1 1 reserved
adt7490 rev. 0 | page 28 of 76 therm as an input when therm is configured as an input, the user can time assertions on the therm pin. this can be useful for connect- ing to the prochot output of a cpu to gauge system performance. the user can also set up the adt7490 so that the fans run at 100% when the therm pin is driven low externally,. the fans run at 100% for the duration of the time that the therm pin is pulled low. this is done by setting the boost bit (bit 2) in configuration register 3 (address 0x78) to 1. this works only if the fan is already running, for example, in manual mode when the current duty cycle is above 0x00, or in automatic mode when the temperature is above t min . if the temperature is below t min or if the duty cycle in manual mode is set to 0x00, pulling the therm low externally has no effect. see figure 33 for more information. therm t min therm asserted to low as an input: fans do not go to 100%, because temperature is below t min . therm asserted to low as an input: fans do not go to 100%, because temperature is above t min and fans are already running. 06789-032 figure 33. asserting therm low as an input in automatic fan speed control mode therm timer the adt7490 has an internal timer to measure therm assertion time. for example, the therm input can be con- nected to the prochot output of a cpu to measure system performance. the therm input can also be connected to the output of a trip point temperature sensor. the timer is started on the assertion of the adt7490s therm input and stopped when therm is deasserted. the timer counts therm times cumulatively, that is, the timer resumes counting on the next therm assertion. the therm timer continues to accumulate therm assertion times until the timer is read (it is cleared on read), or until it reaches full scale. if the counter reaches full scale, it stops at that reading until cleared. the 8-bit therm timer status register (0x79) is designed so that bit 0 is set to 1 on the first therm assertion. once the cumulative therm assertion time has exceeded 45.52 ms, bit 1 of the therm timer is set and bit 0 now becomes the lsb of the timer with a resolution of 22.76 ms (see figure 34 ). therm therm timer (reg. 0x79) therm asserted 22.76ms 765 3210 4 000 0001 0 therm timer (reg. 0x79) therm asserted 45.52ms 765 3210 4 000 0010 0 therm timer (reg. 0x79) therm asserted 113.8ms (91.04ms + 22.76ms) 765 3210 4 000 0101 0 therm accumulate therm low assertion times therm accumulate therm low assertion times 06789-033 figure 34. understanding the therm timer when using the therm timer, be aware of the following. after a therm timer read (register 0x79): x the contents of the timer are cleared on read. x bit 5 of interrupt status 2 register (0x42) needs to be cleared (assuming that the therm timer limit has been exceeded). if the therm timer is read during a therm assertion, the following happens: x the contents of the timer are cleared. x bit 0 of the therm timer is set to 1, because a therm assertion is occurring. x the therm timer increments from zero. x if the therm timer limit (register 0x7a) = 0x00, the f4p bit is set. generating smbalert interrupts from therm timer events the adt7490 can generate smbalert s when a programma- ble therm timer limit has been exceeded. this allows the system designer to ignore brief, infrequent therm assertions while capturing longer therm timer events. register 0x7a is the therm timer limit register. this 8-bit register allows a limit from 0 sec (first therm assertion) to 5.825 sec to be set before an smbalert is generated. the therm timer value is compared with the contents of the therm timer limit register. if the therm timer value exceeds the therm timer limit
adt7490 rev. 0 | page 29 of 76 this allows fail-safe system cooling. if this bit = 0, the fans run at their current settings and are not affected by therm events. if the fans are not already running when therm is asserted, the fans do not run to full speed. value, the fan4 bit (bit 5) of status register 2 is set and an smbalert is generated. note that depending on which pins are configured as a therm timer, setting the f4p bit (bit 5) of the interrupt mask register 2 (0x75), or bit 0 of the interrupt mask register 1 (0x74), masks out smbalert ; although the fan4 bit of interrupt status register 2 is still set if the therm timer limit is exceeded. 3. select whether therm timer events should generate smbalert interrupts. bit 5 of interrupt mask register 2 (0x75) or bit 0 of interrupt mask register 1 (0x74), depending on which pins are configured as a therm timer, when set, masks out smbalert s when the therm timer limit value is exceeded. this bit should be cleared if smbalert s based on therm events are required. figure 35 is a functional block diagram of the therm timer, therm limit, and its associated circuitry. writing a value of 0x00 to the therm timer limit register (register 0x7a) causes an smbalert to be generated on the first therm assertion. a therm timer limit value of 0x01 generates an smbalert once cumulative therm assertions exceed 45.52 ms. 4. select a suitable therm limit value. this value determines whether an smbalert is gener- ated on the first therm assertion, or only if a cumulative therm assertion time limit is exceeded. a value of 0x00 causes an smbalert to be generated on the first therm assertion. configuring the relevant therm behavior 1. configure the desired pin as the therm timer input. setting bit 1 ( therm timer enable) of configuration register 3 (register 0x78) enables the therm timer monitoring functionality. this is disabled on pin 14 and pin 22 by default. setting bit 0 and bit 1 (pin 14 func) of configuration register 4 (register 0x7d) enables therm timer output functionality on pin 22 (bit 1 of configuration register 3, therm , must also be set). pin 14 can also be used as tach4. 5. select a therm monitoring time. this value specifies how often os- or bios-level software checks the therm timer. for example, bios can read the therm timer once an hour to determine the cumulative therm assertion time. if, for example, the total therm assertion time is <22.76 ms in hour 1, >182.08 ms in hour 2, and >5.825 sec in hour 3, this indicates that system per- formance is degrading significantly because therm is asserting more frequently on an hourly basis. 2. select the desired fan behavior for therm timer events. assuming the fans are running, setting bit 2 (boost bit) of configuration register 3 (register 0x78) causes all fans to run at 100% duty cycle whenever therm is asserted. 22.76ms 45.52ms 91.04ms 182.08ms 364.16ms 728.32ms 1.457s 2.914s in out reset latch cleared on read fan4 bit (bit 5) interrupt mask register 2 (register 0x75) 1 = mask fan4 bit (bit 5) interrupt status 2 register comparator 22.76ms 45.52ms 91.04ms 182.08ms 364.16ms 728.32ms 1.457s 2.914s 7 6 543 2 1 0 7 6 543 2 1 0 therm timer limit (register 0x7a) therm timer status (register 0x79) therm timer cleared on read smbalert therm 06789-034 figure 35. functional block diagram of therm monitoring circuitry
adt7490 rev. 0 | page 30 of 76 alternatively, os- or bios-level software can timestamp when the system is powered on. if an smbalert is generated due to the therm timer limit being exceeded, another timestamp can be taken. the difference in time can be calculated for a fixed therm timer limit time. for example, if it takes one week for a therm timer limit of 2.914 sec to be exceeded, and the next time it takes only 1 hour, this is an indication of a serious degrada- tion in system performance. configuring the therm pin as an output in addition to monitoring therm as an input, the adt7490 can optionally drive therm low as an output. when prochot is bidirectional, therm can be used to throttle the processor by asserting prochot . the user can preprogram system-critical thermal limits. if the temperature exceeds a thermal limit by 0.25c, therm asserts low. if the temperature is still above the thermal limit on the next monitoring cycle, therm stays low. therm remains asserted low until the temperature is equal to or below the thermal limit. because the temperature for that channel is measured only once for every monitoring cycle, after therm asserts, it is guaranteed to remain low for at least one monitoring cycle. the therm pin can be configured to assert low if the remote 1 therm , local therm , remote 2 therm or peci tempera- ture limits are exceeded by 0.25c. the therm temperature limit registers are at register 0x6a, register 0x6b, and register 0x6c, respectively. setting bits [5:7] of configuration register 5 (0x7c) enables the therm output feature for the remote 1, local, and remote 2 temperature channels, respectively. figure 36 shows how the therm pin asserts low as an output in the event of a critical overtemperature. monitoring cycle temp therm limit 0.25c therm limit t herm 06789-035 figure 36. asserting therm as an output, based on tripping therm limits an alternative method of disabling therm is to program the therm temperature limit to C63c or less in offset 64 mode, or ?128c or less in twos complement mode; that is, for therm temperature limit values less than C63c or C128c, respectively, therm is disabled. enabling and disabling therm on individual channels the therm pin can be enabled/disabled for individual or combinations of temperature channels using bits [7:5] of configuration register 5 (0x7c). therm hysteresis setting bit 0 of configuration register 7 (0x11) disables therm hysteresis. if therm hysteresis is enabled and therm is disabled (bit 2 of configuration register 4, 0x7d), the therm event is not reflected in the status register and the fans do not go to full speed. if therm hysteresis is disabled and therm is disabled (bit 2 of configuration register 4, 0x7d) and assuming the appropriate pin is configured as therm , the therm pin asserts low when a therm event occurs. if therm and therm hysteresis are both enabled, the therm output asserts as expected. therm operation in manual mode in manual mode, therm events do not cause fans to go to full speed, unless bit 5 of configuration register 1 (0x40) is set to 1. additionally, bit 3 of configuration register 4 (0x7d) can be used to select pwm speed on therm event (100% or maximum pwm). bit 2 in configuration register 4 (0x7d) can be set to disable therm events from affecting the fans. fan drive using pwm control the adt7490 uses pulse-width modulation (pwm) to control fan speed. this relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. the external circuitry required to drive a fan using pwm control is extremely simple. for 4-wire fans, the pwm drive might need only a pull-up resistor. in many cases, the 4-wire fan pwm input has a built-in, pull-up resistor. the adt7490 pwm frequency can be set to a selection of low frequencies or a single high pwm frequency. the low frequency options are used for 3-wire fans, while the high frequency option is usually used with 4-wire fans. for 3-wire fans, a single n-channel mosfet is the only drive device required. the specifications of the mosfet depend on the maximum current required by the fan being driven and the input capacitance of the fet. because a 10 k (or greater) resistor must be used as a pwm pull-up, an fet with large input capacitance can cause the pwm output to become distorted and adversely affect the fan control range. this is a requirement only when using high frequency pwm mode. typical notebook fans draw a nominal 170 ma, therefore, sot devices can be used where board space is a concern. in desktops, fans typically draw 250 ma to 300 ma each. if several fans are driven in parallel from a single pwm output or drive
adt7490 rev. 0 | page 31 of 76 larger server fans, the mosfet must handle the higher current requirements. the only other stipulation is that the mosfet should have a gate voltage drive, v gs < 3.3 v, for direct interfacing to the pwm output pin. the mosfet should also have a low on resistance to ensure that there is not a significant voltage drop across the fet, which would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. figure 37 shows how to drive a 3-wire fan using pwm control. adt7490 tach pwm 12v fan q1 ndt3055l tach 3.3v 12 v 12 v 10k ? 4.7k ? 10k ? 10k ? 1n4148 0 6789-036 figure 37. driving a 3-wire fan using an n-channel mosfet figure 37 uses a 10 k pull-up resistor for the tach signal. this assumes that the tach signal is an open-collector from the fan. in all cases, the tach signal from the fan must be kept below 3.6 v maximum to prevent damaging the adt7490. figure 38 shows a fan drive circuit using an npn transistor such as a general-purpose mmbt2222. while these devices are inexpensive, they tend to have much lower current han- dling capabilities and higher on resistance than mosfets. when choosing a transistor, care should be taken to ensure that it meets the fans current requirements. ensure that the base resistor is chosen so the transistor is saturated when the fan is powered on. adt7490 tach tach pwm 12v fan q1 mmbt2222 3.3v 12 v 12 v 470? 4.7k ? 10k? 10k? 1n4148 06789-037 figure 38. driving a 3-wire fan using an npn transistor because the fan drive circuitry in 4-wire fans is not switched on or off, as with previous pwm driven/powered fans, the internal drive circuit is always on and uses the pwm input as a signal instead of a power supply. this enables the internal fan drive circuit to perform better than 3-wire fans, especially for high frequency applications. figure 39 shows a typical drive circuit for 4-wire fans. adt7490 tach pwm 12v, 4-wire fan 3.3v 12 v 12 v 2k ? 4.7k ? 10k? 10k ? v cc tach tach pwm 06789-038 figure 39. driving a 4-wire fan driving two fans from pwm3 the adt7490 has four tach inputs available for fan speed measurement, but only three pwm drive outputs. if a fourth fan is being used in the system, it should be driven from the pwm3 output in parallel with the third fan. figure 40 shows how to drive two fans in parallel using low cost npn transistors. figure 41 shows the equivalent circuit using a mosfet. because the mosfet can handle up to 3.5 a, it is simply a matter of connecting another fan directly in parallel with the first. care should be taken in designing drive circuits with transistors and fets to ensure the pwm outputs are not required to source current, and that they sink less than the 5 ma maximum current specified in the data sheet. driving up to three fans from pwm3 tach measurements for fans are synchronized to particular pwm channels; for example, tach1 is synchronized to pwm1. tach3 and tach4 are both synchronized to pwm3, so pwm3 can drive two fans. alternatively, pwm3 can be pro- grammed to synchronize tach2, tach3, and tach4 to the pwm3 output. this allows pwm3 to drive two or three fans. in this case, the drive circuitry looks the same, as shown in figure 40 and figure 41 . the sync bit in register 0x62 enables this function. synchronization is not required in high frequency mode when used with 4-wire fans. sync, e nhanced acoustics re gister 1 (register 0x62) bit 4 (sync) = 1, synchronizes tach2, tach3, and tach4 to pwm3.
adt7490 rev. 0 | page 32 of 76 adt7490 pwm3 3.3v 3.3v 12 v 1n4148 q1 mmbt3904 q2 mmbt2222 q3 mmbt2222 10k? 10k? 2.2k ? 1k? tach3 tach4 3.3v 3.3v 06789-039 figure 40. interfacing two fans in parallel to the pwm3 output using low cost npn transistors adt7490 pwm3 tach3 tach4 3.3v 3.3v 3.3 v +v +v tach tach q1 ndt3055l 1n4148 5v or 12v fan 5v or 12v fan 10k? typical 10k? typical 10k? typical 3.3v 3.3v 06789-040 figure 41. interfacing two fans in parallel to the pwm3 output using a single n-channel mosfet laying out 3-wire fans figure 42 shows how to lay out a common circuit arrangement for 3-wire fans. q1 mmbt2222 r2 r1 r3 r4 pwm 1n4148 3.3v or 5v 12v or 5 v tach 0 6789-041 figure 42. planning for 3-wire fans on a pcb tach inputs pins 9, 11, 12, and 14 (when configured as tach inputs) are high impedance inputs intended for fan speed measurement. signal conditioning in the adt7490 accommodates the slow rise and fall times typical of fan tachometer outputs. the maxi- mum input signal range is 0 v to 3.6 v, even though v cc is 3.3 v. in the event that these inputs are supplied from fan outputs that exceed 0 v to 3.6 v, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. figure 43 to figure 46 show circuits for the most common fan tach outputs. if the fan tach output has a resistive pull-up to v cc , it can be connected directly to the fan input, as shown in figure 43 . 12v v cc pull-up 4.7k ? typ tach output fan speed counter tach adt7490 06789-042 figure 43. fan with tach pull-up to v cc if the fan output has a resistive pull-up to 12 v, or other voltage greater than 3.6 v, the fan output can be clamped with a zener diode, as shown in figure 44 . the zener diode voltage should be chosen so that it is greater than v ih of the tach input but less than 3.6 v, allowing for the voltage tolerance of the zener. a value of between 3 v and 3.6 v is suitable. 12v v cc pull-up 4.7k ? typical tach output fan speed counter tach adt7490 zd1* *choose zd1 voltage approximately 0.8 v cc 0 6789-043 figure 44. fan with tach pull-up to voltage > 3.6 v, for example, 12 v clamped with zener diode if the fan has a strong pull-up (less than 1 k) to 12 v or a totem-pole output, a series resistor can be added to limit the zener current, as shown in figure 45 .
adt7490 rev. 0 | page 33 of 76 5v or 12v v cc pull-up typ <1k ? or totem pole tach output fan speed counter tach adt7490 zd1 zener* fan *choose zd1 voltage approximately 0.8 v cc r1 10k ? 06789-044 figure 45. fan with strong tach pull-up to >v cc or totem-pole output, clamped with zener diode and resistor alternatively, a resistive attenuator can be used, as shown in figure 46 . r1 and r2 should be chosen such that 2 v < v pull-up r2 /( r pull-up + r1 + r2 ) < 3.6 v the fan inputs have an input resistance of nominally 160 k to ground, which should be taken into account when calculating resistor values. with a pull-up voltage of 12 v and pull-up resistor less than 1 k, suitable values for r1 and r2 are 100 k and 40 k, respectively. this gives a high input voltage of 3.42 v. 12v v cc <1k ? tach output fan speed counter tach adt7490 r2 40k? r1 100k ? 0 6789-045 figure 46. fan with strong tach pull-up to >v cc or totem-pole output, attenuated with r1/r2 the fan counter does not count the fan tach output pulses directly because the fan speed could be less than 1000 rpm, and it takes several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on-chip 90 khz oscillator into the input of a 16-bit counter for n periods of the fan tach output (see figure 47 ), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. n, the number of pulses counted, is determined by the settings of the tach pulses per revolution register (0x7b). this register contains two bits for each fan, allowing one, two (default), three, or four tach pulses to be counted. 1 2 3 4 clock pwm tach 0 6789-046 figure 47. fan speed measurement fan speed measurement registers the fan tachometer registers are 16-bit values consisting of a 2-byte read from the adt7490. register 0x28, tach1 low byte = 0x00 default register 0x29, tach1 high byte = 0x00 default register 0x2a, tach2 low byte = 0x00 default register 0x2b, tach2 high byte = 0x00 default register 0x2c, tach3 low byte = 0x00 default register 0x2d, tach3 high byte = 0x00 default register 0x2e, tach4 low byte = 0x00 default register 0x2f, tach4 high byte = 0x00 default reading fan speed from the adt7490 the measurement of fan speeds involves a 2-register read for each measurement. the low byte should be read first. this causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous tach readings. the fan tachometer reading registers report back the number of 11.11 s period clocks (90 khz oscillator) gated to the fan speed counter, from the rising edge of the first fan tach pulse to the rising edge of the third fan tach pulse (assuming two pulses per revolution are being counted). because the device is essentially measuring the fan tach period, the higher the count value, the slower the fan is actu- ally running. a 16-bit fan tachometer reading of 0xffff indicates that either the fan has stalled or is running very slowly (<100 rpm). high limit > comparison performed because the actual fan tach period is being measured, falling below a fan tach limit by 1 sets the appropriate status bit and can be used to generate an smbalert . fan tach limit registers the fan tach limit registers are 16-bit values consisting of two bytes. register 0x54, tach1 minimum low byte = 0xff default register 0x55, tach1 minimum high byte = 0xff default register 0x56, tach2 minimum low byte = 0xff default register 0x57, tach2 minimum high byte = 0xff default register 0x58, tach3 minimum low byte = 0xff default register 0x59, tach3 minimum high byte = 0xff default register 0x5a, tach4 minimum low byte = 0xff default register 0x5b, tach4 minimum high byte = 0xff default
adt7490 rev. 0 | page 34 of 76 fan speed measurement rate the fan tach readings are normally updated once every second. when set, the fast bit (bit 3) of configuration register 3 (0x78), updates the fan tach readings every 250 ms. dc bits if any of the fans are not being driven by a pwm channel but are powered directly from 5 v or 12 v, their associated dc bit in configuration register 3 should be set. this allows tach readings to be taken on a continuous basis for fans connected directly to a dc source. for 4-wire fans, once high frequency mode is enabled, the dc bits do not need to be set because this is automatically done internally. calculating fan speed assuming a fan with a two pulses per revolution, and with the adt7490 programmed to measure two pulses per revolution, fan speed is calculated by fan speed (rpm) = (90,000 60)/ fan tach reading where fan tach reading is the 16-bit fan tachometer reading. example tach1 high byte (register 0x29) = 0x17 tach1 low byte (register 0x28) = 0xff what is fan 1 speed in rpm? fan 1 tach reading = 0x17ff = 6143 (decimal) rpm = (f 60)/ fan 1 tach reading rpm = (90000 60)/6143 fan speed = 879 rpm fan pulses per revolution different fan models can output either one, two, three, or four tach pulses per revolution. once the number of fan tach pulses has been determined, it can be programmed into the tach pulses per revolution register (0x7b) for each fan. alternatively, this register can be used to determine the number or pulses per revolution output by a given fan. by plotting fan speed measurements at 100% speed with different pulses per revolution setting, the smoothest graph with the lowest ripple determines the correct pulses per revolution value. tach pulses per revolution register bits [1:0], fan1 default = 2 pulses per revolution bits [3:2], fan2 default = 2 pulses per revolution bits [5:4], fan3 default = 2 pulses per revolution bits [7:6], fan4 default = 2 pulses per revolution 00 = 1 pulse per revolution 01 = 2 pulses per revolution 10 = 3 pulses per revolution 11 = 4 pulses per revolution fan spin-up the adt7490 has a unique fan spin-up function. it spins the fan at 100% pwm duty cycle until two tach pulses are detected on the tach input. when two tach pulses have been detected, the pwm duty cycle goes to the expected running value, for example, 33%. the advantage of this is that fans have different spin-up characteristics and take different times to overcome inertia. the adt7490 runs the fans just fast enough to overcome inertia and is quieter on spin-up than fans programmed to spin up for a given spin-up time. fan start-up timeout to prevent the generation of false interrupts as a fan spins up, because the fan is below running speed, the adt7490 includes a fan start-up timeout function. during this time, the adt7490 looks for two tach pulses. if two tach pulses are not detected, an interrupt is generated. fan start-up timeout can be disabled by setting bit 3 (fspdis) of configuration register 7 (0x11). pwm1, pwm2, pwm3 configuration (register 0x5c, register 0x5d, register 0x5e) bits [2:0] spin, start-up timeout for pwm1 = 0x5c, pwm2 = 0x5d, and pwm3 = 0x5e. 000 = no start-up timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec disabling fan start-up timeout although fan startup makes fan spin-ups much quieter than fixed-time spin-ups, the option exists to use fixed spin-up times. setting bit 3 (fspdis) to 1 in configuration register 7 (register 0x11) disables the spin-up for two tach pulses. instead, the fan spins up for the fixed time as selected in register 0x5c to register 0x5e. pwm logic state the pwm outputs can be programmed high for 100% duty cycle (noninverted) or low for 100% duty cycle (inverted). pwm1 configuration (register 0x5c) bit 4 (inv) 0 = logic high for 100% pwm duty cycle (noninverted) 1 = logic low for 100% pwm duty cycle (inverted) pwm2 configuratio n (register 0x5d) bit 4 (inv) 0 = logic high for 100% pwm duty cycle 1 = logic low for 100% pwm duty cycle
adt7490 rev. 0 | page 35 of 76 pwm3 configuration (register 0x5e) pwm configuration registers (register 0x5c to register 0x5e) bit 4 (inv) bits [7:5] (bhvr) 0 = logic high for 100% pwm duty cycle (noninverted). 1 = logic low for 100% pwm duty cycle (inverted). 111 = manual mode low frequency mode pwm drive frequency once under manual control, each pwm output can be manu- ally updated by writing to register 0x30 to register 0x32 (pwmx current duty cycle registers). the pwm drive frequency can be adjusted for the application. register 0x5f to register 0x61 configure the pwm frequency for pwm1 to pwm3, respectively. programming the pwm current duty cycle registers pwm1, pwm 2, pwm3 frequency registers (register 0x5f to register 0x61) the pwm current duty cycle registers are 8-bit registers that allow the pwm duty cycle for each output to be set anywhere from 0% to 100% in steps of 0.39%. the value to be programmed into the pwm min register is given by bits [2:0] freq 000 = 11.0 hz 001 = 14.7 hz 010 = 22.1 hz 011 = 29.4 hz 100 = 35.3 hz default 101 = 44.1 hz 110 = 58.8 hz 111 = 88.2 hz value (decimal) = pwm min /0.39 example 1 for a pwm duty cycle of 50%, value (decimal) = 50/0.39 = 128 (decimal) value = 128 (decimal) or 0x80 (hex) example 2 high frequency mode pwm drive for a pwm duty cycle of 33%, setting bit 3 of register 0x5f, register 0x60, and register 0x61 enables high frequency mode for fan 1, fan 2, and fan 3, respectively. value (decimal) = 33/0.39 = 85 (decimal) value = 85 (decimal) or 0x54 (hex) pwm duty cycle registers in high frequency mode, the pwm drive frequency is always 22.5 khz. when high frequency mode is enabled, the dc bits are automatically asserted internally and do not need to be changed. register 0x30, pwm1 duty cycle = 0xff (100% default) register 0x31, pwm2 duty cycle = 0xff (100% default) register 0x32, pwm3 duty cycle = 0xff (100% default) fan speed control by reading the pwmx current duty cycle registers, the user can keep track of the current duty cycle on each pwm output, even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. the adt7490 controls fan speed using automatic and manual modes. in automatic fan speed control mode, fan speed is automatically varied with temperature and without cpu intervention, once initial parameters are set up. the advantage is that, if the system hangs, the user is guaranteed that the system is protected from overheating. programming t range t range defines the distance between t min and 100% pwm. for the adt7467, adt7468 and adt7473, t range is effectively a slope. for the adt7475, adt7476 and adt7490, t range is no longer a slope but defines the temperature region where the pwm output linearly ramps from pwm min to 100% pwm. in manual fan speed control mode, the adt7490 allows the duty cycle of any pwm output to be manually adjusted. this can be useful if the user wants to change fan speed in software or adjust pwm duty cycle output for test purposes. bits [7:5] of register 0x5c to register 0x5e (pwm configuration) control the behavior of each pwm output. t min pwm = 100% pwm min pwm max pwm = 0% t range 0 6789-047 figure 48. t range
adt7490 rev. 0 | page 36 of 76 programming the automatic fan speed control loop to more efficiently understand the automatic fan speed control loop, using the adt7490 evaluation board and software while reading this section is recommended. this section provides the system designer with an understanding of the automatic fan control loop, and provides step-by-step guidance on effectively evaluating and selecting critical system parameters. to optimize the system characteristics, the designer needs to give some thought to system configuration, including the number of fans, where they are located, and what tempera- tures are being measured in the particular system. the mechanical or thermal engineer who is tasked with the system thermal characterization should also be involved at the beginning of the system development process. manual fan control overview in unusual circumstances, it can be necessary to manually control the speed of the fans. because the adt7490 has an smbus interface, a system can read back all necessary voltage, fan speed, and temperature information, and use this information to control the speed of the fans by writing to the current pwm duty cycle register (0x30, 0x31, and 0x32) of the appropriate fan. bits [7:5] of the pwmx configuration registers (0x5c, 0x5d, and 0x5e) are used to set fans up for manual control. therm operation in manual mode in manual mode, if the temperature increases above the pro- grammed therm temperature limit, the fans automatically speed up to maximum pwm or 100% pwm, whichever way the appropriate fan channel is configured. automatic fan control overview the adt7490 can automatically control the speed of fans based on the measured temperature. this is done independently of cpu intervention once the initial parameters are set up. the adt7490 has a local temperature sensor and two remote temperature channels that can be connected to a cpu on-chip thermal diode (available on intel pentium? class and other cpus). these three temperature channels can be used as the basis for automatic fan speed control to drive fans using pulse- width modulation (pwm). automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature. reducing fan speed can also decrease system current consump- tion. the automatic fan speed control mode is very flexible due to the number of programmable parameters, including t min and t range . the t min and t range values for a temperature channel and, therefore, for a given fan are critical, because they define the thermal characteristics of the system. the thermal validation of the system is one of the most important steps in the design process, so these values should be selected carefully. figure 49 gives a top-level overview of the automatic fan control circuitry on the adt7490. from a systems-level perspective, up to three system temperatures can be monitored and used to control three pwm outputs. the three pwm outputs can be used to control up to four fans. the adt7490 allows the speed of four fans to be monitored. each temperature channel has a thermal calibration block, allowing the designer to individually configure the thermal characteristics of each temperature channel. for example, users can decide to run the cpu fan when cpu temperature increases above 60c and a chassis fan when the local temperature increases above 45c. at this stage, the designer has not assigned these thermal calibration settings to a particular fan drive (pwm) channel. the right side of figure 49 shows controls that are fan-specific. the designer has individual control over parameters such as minimum pwm duty cycle, fan speed failure thresholds, and even ramp control of the pwm outputs. automatic fan control ultimately allows graceful fan speed changes that are less perceptible to the system user.
adt7490 rev. 0 | page 37 of 76 rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 2 = gpu temp remote 1 = ambient temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm min pwm min 100% peci = cpu temp thermal calibration 0% t min t range 100% ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator pwm generator tachometer 3 and 4 measurement tachometer 1 measurement tachometer 2 measurement pwm generator pwm config pwm config pwm config 06789-067 figure 49. automatic fan control block diagram step 1: hardware configuration during system design, the motherboard sensing and control capabilities should be addressed early in the design stages. decisions about how these capabilities are used should involve the system thermal/mechanical engineer. ask the following questions: 1. what adt7490 functionality is used? ? pwm2 or smbalert ? ? tach4 fan speed measurement or overtemperature therm function? ? 2.5 v in voltage monitoring or overtemperature therm function? the adt7490 offers multifunctional pins that can be reconfigured to suit different system requirements and physical layouts. these multifunction pins are software programmable. 2. how many fans are supported in the system, three or four? this influences the choice of whether to use the tach4 pin or to reconfigure it for the therm function. 3. is the cpu fan to be controlled using the adt7490, or will the cpu fan run at full speed 100% of the time? if run at 100%, it frees up a pwm output, but the system is louder. 4. where is the adt7490 going to be physically located in the system? this influences the assignment of the temperature meas- urement channels to particular system thermal zones. for example, locating the adt7490 close to the vrm controller circuitry allows the vrm temperature to be monitored using the local temperature channel. step 2: configuring the muxtiplexer after the system hardware configuration is determined, the fans can be assigned to particular temperature channels. not only can fans be assigned to individual channels, but the behavior of the fans is also configurable. for example, fans can be run under automatic fan control, can be run manually (under software control), or can be run at the fastest speed calcu- lated by multiple temperature channels. the mux is the bridge between temperature measurement channels and the three pwm outputs. bits [7:5] (bhvr) of register 0x5c, register 0x5d, and register 0x5e (pwm configuration registers) control the behavior of the fans connected to the pwm1, pwm2, and pwm3 outputs, respectively. the values selected for these bits determine how the multiplexer connects a temperature measurement channel to a pwm output.
adt7490 rev. 0 | page 38 of 76 automatic fan control multiplexer options bits [ 7:5] ( bhvr ), register 0x5c, register 0x5d, and register 0x5e, with the alt bit (bit 3) cleared to 0. 000 = remote 1 temperature controls pwmx 001 = local temperature controls pwmx 010 = remote 2 temperature controls pwmx 101 = fastest speed calculated by local and remote 2 temperature controls pwmx 110 = fastest speed calculated by all three temperature channels controls pwmx the fastest speed calculated options pertain to controlling one pwm output based on multiple temperature channels. the thermal characteristics of the three temperature zones can be set to drive a single fan. an example is the fan turning on when remote 1 temperature exceeds 60c or if the local temperature exceeds 45c. setting the alt bit in register 0x5c, register 0x5d, and register 0x5e gives alternative behavior settings for bits [7:5] of the pwm configuration registers. bits [7:5] (bhvr), register 0x5c, register 0x5d, and register 0x5e, with the alt bit (bit 3) set to 1. 000 = peci0 reading controls pwmx 001 = peci1 reading controls pwmx 010 = peci2 reading controls pwmx 011 = peci3 reading controls pwmx 101 = fastest speed calculated by all four peci readings controls pwmx 111 = fastest speed calculated by all thermal zones (local, rem1, rem2 and peci) controls pwmx other mux options bits [7:5] (bhvr), register 0x5c, register 0x5d, and register 0x5e, with the alt bit (bit 3) cleared to 0. 011 = pwmx runs full speed 100 = pwmx disabled (default) 111 = manual mode. pwmx is running under software control. in this mode, pwm duty cycle registers (register 0x30 to register 0x32) are writable and control the pwm outputs. bits [7:5] (bhvr) , register 0x5c, register 0x5d, and register 0x5e, with alt bit (bit 3) set to 1. 100 = pwmx runs at 100% duty cycle 110 = pwmx runs at 100% duty cycle step 3: t min settings for thermal calibration channels t min is the temperature at which the fans start to turn on under automatic fan control. the speed at which the fan runs at t min is programmed later. the t min values chosen are temperature channel specific, for example, 25c for ambient channel, 30c for vrm temperature, and 40c for processor temperature. t min is an 8-bit value, either twos complement or offset 64, that can be programmed in 1c increments. a t min register is associated with each temperature measurement channel: remote 1, local, remote 2 and peci temperature. when the t min value is exceeded, the fan turns on and runs at the mini- mum pwm duty cycle. the fan turns off once the temperature has dropped below t min ? t hyst . to overcome fan inertia, the fan is spun up until two valid tach rising edges are counted. see the fan start-up timeout section for more details. in some cases, primarily for psycho-acoustic reasons, it is desirable that the fan never switch off below t min . when set, bits [7:5] of enhanced acoustics register 1 (0x62) keep the fans running at the pwm minimum duty cycle, if the temperature should fall below t min . t min registers register 0x67, remote 1 temperature t min = 0x5a (90c default) register 0x68, local temperature t min = 0x5a (90c default) register 0x69, remote 2 temperature t min = 0x5a (90c default) register 0x3b, peci t min = 0xe0 (?32c default) enhanced acoustics regi ster 1 (register 0x62) bit 7 (min3) = 0, pwm3 is off (0% pwm duty cycle) when temperature is below t min C t hyst . bit 7 (min3) = 1, pwm3 runs at pwm3 minimum duty cycle below t min C t hyst . bit 6 (min2) = 0, pwm2 is off (0% pwm duty cycle) when temperature is below t min C t hyst . bit 6 (min2) = 1, pwm2 runs at pwm2 minimum duty cycle below t min C t hyst . bit 5 (min1) = 0, pwm1 is off (0% pwm duty cycle) when temperature is below t min C t hyst . bit 5 (min1) = 1, pwm1 runs at pwm1 minimum duty cycle below t min C t hyst .
adt7490 rev. 0 | page 39 of 76 rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm min pwm min 100% ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator pwm generator tachometer 3 and 4 measurement tachometer 1 measurement tachometer 2 measurement pwm generator pwm config pwm config pwm config 06789-068 0% 100% p w m d u t y c y c l e t min figure 50. understanding the t min parameter
adt7490 rev. 0 | page 40 of 76 step 4: pwm min for each pwm (fan) output pwm min is the minimum pwm duty cycle at which each fan in the system runs. it is also the start speed for each fan under automatic fan control once the temperature rises above t min . for maximum system acoustic benefit, pwm min should be as low as possible. depending on the fan used, the pwm min set- ting is usually in the 20% to 33% duty cycle range. this value can be found through fan validation. temperature t min 100% pwm min 0% pwm duty cycle 06789-055 figure 51. pwm min determines minimum pwm duty cycle more than one pwm output can be controlled from a single temperature measurement channel. for example, remote 1 temperature can control pwm1 and pwm2 outputs. if two different fans are used on pwm1 and pwm2, the fan characteristics can be set up differently. as a result, fan 1 driven by pwm1 can have a different pwm min value than that of fan 2 connected to pwm2. figure 52 illustrates this as pwm1 min (front fan) turned on at a minimum duty cycle of 20%, while pwm2 min (rear fan) is turned on at a minimum of 40% duty cycle. note that both fans turn on at exactly the same temperature, defined by t min . temperature t min 100% pwm1 min 0% pwm duty cycle p w m 1 p w m 2 pwm2 min 06789-056 figure 52. operating two different fans from a single temperature channel programming the pwm min registers the pwm min registers are 8-bit registers that allow the mini- mum pwm duty cycle for each output to be configured anywhere from 0% to 100%. this allows the minimum pwm duty cycle to be set in steps of 0.39%. the value to be programmed into the pwm min register is given by value (decimal) = pwm min /0.39 example 1 for a minimum pwm duty cycle of 50%, value (decimal) = 50/0.39 = 128 (decimal) value = 128 (decimal) or 0x80 (hex) example 2 for a minimum pwm duty cycle of 33%, value (decimal) = 33/0.39 = 85 (decimal) value = 85 (decimal) or 0x54 (hex) pwm min registers register 0x64, pwm1 minimum duty cycle = 0x80 (50% default) register 0x65, pwm2 minimum duty cycle = 0x80 (50% default) register 0x66, pwm3 minimum duty cycle = 0x80 (50% default) note on fan speed and pwm duty cycle the pwm duty cycle does not directly correlate to fan speed in rpm. running a fan at 33% pwm duty cycle does not equate to running the fan at 33% speed. driving a fan at 33% pwm duty cycle actually runs the fan at closer to 50% of its full speed. this is because fan speed in %rpm generally relates to the square root of pwm duty cycle. given a pwm square wave as the drive signal, fan speed in rpm approximates to 10 % = cycledutypwm fanspeed step 5: pwm max for pwm (fan) outputs pwm max is the maximum duty cycle that each fan in the system runs at under the automatic fan speed control loop. for maxi- mum system acoustic benefit, pwm max should be as low as possible, but should be capable of maintaining the processor temperature limit at an acceptable level. if the therm temperature limit is exceeded, the fans are still boosted to 100% for fail-safe cooling. there is a pwm max limit for each fan channel. the default value of this register is 0xff and has no effect unless it is programmed. temperature t min 100% pwm min 0% pwm duty cycle pwm max 06789-057 figure 53. pwm max determines maximum pwm duty cycle below the therm temperature limit
adt7490 rev. 0 | page 41 of 76 programming the pwm max registers the pwm max registers are 8-bit registers that allow the maximum pwm duty cycle for each output to be configured anywhere from 0% to 100%. this allows the maximum pwm duty cycle to be set in steps of 0.39%. the value to be programmed into the pwm max register is given by value (decimal) = pwm max /0.39 example 1 for a maximum pwm duty cycle of 50%, value (decimal) C 50/0.39 = 128 (decimal) value = 128 (decimal) or 0x80 (hex) example 2 for a minimum pwm duty cycle of 75%, value (decimal) = 75/0.39 = 85 (decimal) value = 192 (decimal) or 0xc0 (hex) pwm max registers register 0x38, maximum pwm1 duty cycle = 0xff (100% default) register 0x39, maximum pwm2 duty cycle = 0xff (100% default) register 0x3a, maximum pwm3 duty cycle = 0xff (100% default) step 6: t range for temperature channels t range is the range of temperature over which automatic fan control occurs once the programmed t min temperature has been exceeded. t range is the temperature range between pwm min and 100% pwm where the fan speed changes linearly. otherwise stated, it is the line drawn between the t min /pwm min and the (t min + t range )/100% pwm intersection points. temperature t min 100% pwm min 0% pwm duty cycle t range 06789-058 figure 54. t range parameter affects cooling slope the t range is determined by the following procedure: 1. determine the maximum operating temperature for that channel (for example, 70c). 2. determine experimentally the fan speed (pwm duty cycle value) that does not exceed the temperature at the worst- case operating points. for example, 70c is reached when the fans are running at 50% pwm duty cycle. 3. determine the slope of the required control loop to meet these requirements. 4. using the adt7490 evaluation software, graphically program and visualize this functionality. ask a local analog devices representative for details. as pwm min is changed, the automatic fan control slope changes. t min 100% 33% 0% pwm duty cycle 50% 30c 06789-059 figure 55. adjusting pwm min changes the automatic fan control slope as t range is changed, the slope changes. as t range gets smaller, the fans reach 100% speed with a smaller temperature change. t min t min?hyst 100% 0% pwm duty cycle 30c 40c 10% 45c 54c 06789-060 figure 56. increasing t range changes the afc slope 100% max pwm 0% pwm duty cycle t range 10% t min?hyst 0 6789-061 figure 57. changing pwm max does not change the afc slope
adt7490 rev. 0 | page 42 of 76 selecting t range the t range value can be selected for each temperature channel: remote 1, local, remote 2, and peci temperature. bits [7:4] (t range ) of register 0x5f to register 0x61 and register 0x3c define the t range value for each temperature channel. table 23. selecting a t range value bits [7:4] 1 t range (c) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 (default) 1101 40 1110 53.33 1111 80 1 register 0x5f configures remote 1 t range ; register 0x60 configures local t range ; register 0x61 configures remote 2 t range , register 0x3c configures peci t range . actual changes in pwm output (advanced acoustics settings) while the automatic fan control algorithm describes the general response of the pwm output, it is also necessary to note that the enhanced acoustics registers (0x62, 0x63, and 0x3c) can be used to set/clamp the maximum rate of change of pwm output for a given temperature zone. this means that if t range is pro- grammed with an afc slope that is quite steep, a relatively small change in temperature could cause a large change in pwm output and possibly an audible change in fan speed, which can be noticeable/annoying to end users. decreasing the speed of the pwm output changes by programming the smoothing on the appropriate temperature channels (register 0x62 and register 0x63) changes how fast the fan speed increases/decreases in the event of a temperature spike. slowly the pwm duty cycle increases until the pwm duty cycle reaches the appropriate duty cycle as defined by the afc curve. figure 58 shows pwm duty cycle vs. temperature for each t range setting. figure 58 b shows how each t range setting affects fan speed vs. temperature. as can be seen from the graph, the effect on fan speed is nonlinear. temperature above t min 0 20406080100120 0 fan speed (% of max) 10 20 30 40 50 60 70 80 90 100 temperature above t min (b) (a) 0 20 40 60 80 100 120 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 2 c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 06789-062 figure 58. t range vs. actual fan speed (not pwm drive) profile the graphs in figure 58 assume the fan starts from 0% pwm duty cycle. clearly, the minimum pwm duty cycle, pwm min , needs to be factored in to see how the loop actually performs in the system. figure 59 shows how t range is affected when the pwm min value is set to 20%. it can be seen that the fan actually runs at about 45% fan speed when the temperature exceeds t min .
adt7490 rev. 0 | page 43 of 76 temperature above t min 0 20 40 60 80 100 120 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 temperature above t min (a) (b) 0 20406080100120 0 fan speed (% of max) 10 20 30 40 50 60 70 80 90 100 2 c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 06789-063 figure 59. t range and % fan speed slopes with pwm min = 20% step 7: t therm for temperature channels t therm is the absolute maximum temperature allowed on a temperature channel. for peci temperature channels, the equivalent parameter is t control . above this temperature, a component such as the cpu or vrm may be operating beyond its safe operating limit. when the temperature measured exceeds t therm , all fans are driven at 100% pwm duty cycle (full speed) to provide critical system cooling. the fans remain running at 100% until the temperature drops below t therm minus hysteresis, where hysteresis is the number programmed into the hysteresis registers (0x6d and 0x6e). the default hysteresis value is 4c. the t therm limit should be considered the maximum worst-case operating temperature of the system. because exceeding any t therm limit runs all fans at 100%, it has very negative acoustic effects. ultimately, this limit should be set up as a fail-safe, and one should ensure that it is not exceeded under normal system operating conditions. note that t therm limits are nonmaskable and affect the fan speed no matter how automatic fan control settings are configured. this allows some flexibility, because a t range value can be selected based on its slope, while a hard limit (such as 70c), can be programmed as t max (the temperature at which the fan reaches full speed) by setting t therm to that limit (for example, 70c). therm registers register 0x6a, remote 1 therm temperature limit = 0x64 (100c default) register 0x6b, local therm temperature limit = 0x64 (100c default) register 0x6c, remote 2 therm temperature limit = 0x64 (100c default) register 0x3d, peci t control limit = 0x00 (0c default) therm hysteresis therm hysteresis on a particular channel is configured via the hysteresis settings in the following section (0x6d and 0x6e). for example, setting hysteresis on the remote 1 channel also sets the hysteresis on remote 1 therm . hysteresis registers register 0x6d, remote 1, local hysteresis register bits [7:4], remote 1 temperature hysteresis (4c default). bits [3:0], local temperature hysteresis (4c default). register 0x6e, remote 2, peci temperature hysteresis register bits [7:4], remote 2 temperature hysteresis (4c default). bits [3:0], peci temperature hysteresis (4c default). because each hysteresis setting is four bits, hysteresis values are programmable from 1c to 15c. it is not recommended that hysteresis values ever be programmed to 0c, because this disables hysteresis. in effect, this causes the fans to cycle (during a therm event ) between normal speed and 100% speed, or, while operating close to t min , between normal speed and off, creating unsettling acoustic noise.
adt7490 rev. 0 | page 44 of 76 t min p w m d u t y c y c l e 0% 100% t therm t range rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm generator pwm min pwm generator tachometer 3 and 4 measurement pwm min tachometer 1 measurement tachometer 2 measurement ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator 100% pwm config pwm config pwm config 0 6789-065 figure 60. how t therm relates to automatic fan control step 8: t hyst for temperature channels t hyst is the amount of extra cooling a fan provides after the temperature measured has dropped back below t min before the fan turns off. the premise for temperature hysteresis (t hyst ) is that, without it, the fan would merely chatter, or cycle on and off regularly, whenever the temperature is hovering at about the t min setting. the t hyst value chosen determines the amount of time needed for the system to cool down or heat up as the fan is turning on and off. values of hysteresis are programmable in the range of 1c to 15c. larger values of t hyst prevent the fans from chattering on and off. the t hyst default value is set at 4c. the t hyst setting applies not only to the temperature hysteresis for fan on/off, but the same setting is used for the t therm hysteresis value, described in the step 7: t therm for temperature channels section. therefore, programming register 0x6d and register 0x6e sets the hysteresis for both fan on/off and the therm function. in some applications, it is required that fans not turn off below t min , but remain running at pwm min . bits [7:5] of enhanced acoustics register 1 (0x62) allow the fans to be turned off or to be kept spinning below t min . if the fans are always on, the t hyst value has no effect on the fan when the temperature drops below t min .
adt7490 rev. 0 | page 45 of 76 rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm min pwm min 100% t min p w m d u t y c y c l e 0% 100% t range t therm ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator pwm generator tachometer 3 and 4 measurement tachometer 1 measurement tachometer 2 measurement pwm generator pwm config pwm config pwm config 06789-066 figure 61. the t hyst value applies to fan on/off hysteresis and therm hysteresis therm hysteresis any hysteresis programmed via re gister 0x6d and register 0x6e also applies hysteresis on the appropriate therm channel. enhanced acoustics regi ster 1 (register 0x62) bit 7 (min3) = 0, pwm3 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 7 (min3) = 1, pwm3 runs at pwm3 minimum duty cycle below t min ? t hyst . bit 6 (min2) = 0, pwm2 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 6 (min2) = 1, pwm2 runs at pwm2 minimum duty cycle below t min ? t hyst . bit 5 (min1) = 0, pwm1 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 5 (min1) = 1, pwm1 runs at pwm1 minimum duty cycle below t min ? t hyst . configuration register 6 (register 0x10) bit 0 (slow) = 1, slows the ramp rate for pwm changes associated with the remote 1 temperature channel by 4. bit 1 (slow) = 1, slows the ramp rate for pwm changes associated with the local temperature channel by 4. bit 2 (slow) = 1, slows the ramp rate for pwm changes associated with the remote 2 temperature channel by 4. bit 7 (extraslow) = 1, slows the ramp rate for all fans by a factor of 39.2%. the following sections list the ramp-up times when the slow bit is set for each temperature monitoring channel.
adt7490 rev. 0 | page 46 of 76 enhanced acoustics regi ster 1 (register 0x62) bits [2:0] acou, selects the ramp rate for pwm outputs associated with the remote temperature 1 input. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = 4.7 sec 101 = 3.1 sec 110 = 1.6 sec 111 = 0.8 sec enhanced acoustics regi ster 2 (register 0x63) bits [2:0] acou3, selects the ramp rate for pwm outputs associated with the local temperature channel. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = 4.7 sec 101 = 3.1 sec 110 = 1.6 sec 111 = 0.8 sec [6:4] acou2, selects the ramp rate for pwm outputs associated with the remote temperature 2 input. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = 4.7 sec 101 = 3.1 sec 110 = 1.6 sec 111 = 0.8 sec when bit 7 of configuration register 6 (0x10) = 1, the preceding ramp rates change to 000 = 52.2 sec 001 = 26.1 sec 010 = 17.4 sec 011 = 10.4 sec 100 = 6.5 sec 101 = 4.4 sec 110 = 2.2 sec 111 = 1.1 sec setting the appropriate slow bit 2, bit 1, or bit 0 of configuration register 6 (0x10) slows the ramp rate further by a factor of 4. programming the gpio s the adt7490 has two dedicated gpios (pin 5 and pin 6).the direction (input or output) and polarity (active high or active low) of the gpios is set in the gpio configuration register (0x80). bit 2 and bit 3 of register 0x80 also reflect the state of the gpio pins when configured as inputs and assert the gpio pins when configured as outputs. xnor tree test mode the adt7490 includes an xnor tree test mode. this mode is useful for in-circuit test equipment at board-level testing. by applying stimulus to the pins in cluded in the xnor tree, it is possible to detect opens, or shorts, on the system board. the xnor tree test is invoked by setting bit 0 (xen) of the xnor tree test enable register (register 0x6f). figure 62 shows the signals that are exercised in the xnor tree test mode. pwm1/xto pwm3 pwm2 t ach4 t ach3 t ach2 t ach1 06789-004 figure 62. xnor tree test
adt7490 rev. 0 | page 47 of 76 register tables table 24. adt7490 registers addr. r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable? 0x10 r/w config. 6 extraslow v ccp low res res res slow remote 2 slow local slow remote 1 0x00 yes 0x11 r/w config. 7 res res res todis fspdis vx1 fspd thermhys 0x00 yes 0x1a r peci1 7 6 5 4 3 2 1 0 0x80 0x1b r peci2 7 6 5 4 3 2 1 0 0x80 0x1c r peci3 7 6 5 4 3 2 1 0 0x80 0x1d r i mon meas. 9 8 7 6 5 4 3 2 0x00 0x1e r v tt meas. 9 8 7 6 5 4 3 2 0x00 0x1f r extended resolution 3 i mon i mon v tt v tt res res res res 0x00 0x20 r +2.5v in meas. 9 8 7 6 5 4 3 2 0x00 0x21 r v ccp meas. 9 8 7 6 5 4 3 2 0x00 0x22 r v cc meas. 9 8 7 6 5 4 3 2 0x00 0x23 r +5v in meas. 9 8 7 6 5 4 3 2 0x00 0x24 r +12v in meas. 9 8 7 6 5 4 3 2 0x00 0x25 r remote 1 temp. 9 8 7 6 5 4 3 2 0x80 0x26 r local temp. 9 8 7 6 5 4 3 2 0x80 0x27 r remote 2 temp. 9 8 7 6 5 4 3 2 0x80 0x28 r tach1 low byte 7 6 5 4 3 2 1 0 0x00 0x29 r tach1 high byte 15 14 13 12 11 10 9 8 0x00 0x2a r tach2 low byte 7 6 5 4 3 2 1 0 0x00 0x2b r tach2 high byte 15 14 13 12 11 10 9 8 0x00 0x2c r tach3 low byte 7 6 5 4 3 2 1 0 0x00 0x2d r tach3 high byte 15 14 13 12 11 10 9 8 0x00 0x2e r tach4 low byte 7 6 5 4 3 2 1 0 0x00 0x2f r tach4 high byte 15 14 13 12 11 10 9 8 0x00 0x30 r/w pwm1 current duty cycle 7 6 5 4 3 2 1 0 0xff 0x31 r/w pwm2 current duty cycle 7 6 5 4 3 2 1 0 0xff 0x32 r/w pwm3 current duty cycle 7 6 5 4 3 2 1 0 0xff 0x33 r peci0 7 6 5 4 3 2 1 0 0x80 0x34 r/w peci low limit 7 6 5 4 3 2 1 0 0x81 0x35 r/w peci high limit 7 6 5 4 3 2 1 0 0x00 0x36 r/w peci config. register 1 res res res replace dom0 avg2 avg1 avg0 0x00 yes 0x38 r/w max pwm1 duty cycle 7 6 5 4 3 2 1 0 0xff yes 0x39 r/w max pwm2 duty cycle 7 6 5 4 3 2 1 0 0xff yes 0x3a r/w max pwm3 duty cycle 7 6 5 4 3 2 1 0 0xff yes 0x3b r/w peci t min 7 6 5 4 3 2 1 0 0xe0 yes
adt7490 rev. 0 | page 48 of 76 addr. r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable? 0x3c r/w peci t range / enhanced acoustics range range range range enp acou acou acou 0xc0 yes 0x3d r/w peci t control 7 6 5 4 3 2 1 0 0x00 yes 0x3e r company id no. 7 6 5 4 3 2 1 0 0x41 0x3f r version/ revision ver3 ver2 ver1 ver0 4-wire peci rev1 rev0 0x6e 0x40 r/w config. register 1 res res therm in manual peci monitor fan boost rdy lock strt 0x04 yes 0x41 r interrupt status 1 ool r2t lt r1t +5v in v cc v ccp +2.5v in / therm 0x00 0x42 r interrupt status 2 d2 fault d1 fault fan4/ therm fan3 fan2 fan1 ool +12v in 0x00 0x43 r interrupt status 3 ool res res res ovt ( therm temp limit) comm data peci0 0x00 0x44 r/w +2.5v in low limit 7 6 5 4 3 2 1 0 0x00 0x45 r/w +2.5v in high limit 7 6 5 4 3 2 1 0 0xff 0x46 r/w v ccp low limit 7 6 5 4 3 2 1 0 0x00 0x47 r/w v ccp high limit 7 6 5 4 3 2 1 0 0xff 0x48 r/w v cc low limit 7 6 5 4 3 2 1 0 0x00 0x49 r/w v cc high limit 7 6 5 4 3 2 1 0 0xff 0x4a r/w +5v in low limit 7 6 5 4 3 2 1 0 0x00 0x4b r/w +5v in high limit 7 6 5 4 3 2 1 0 0xff 0x4c r/w +12v in low limit 7 6 5 4 3 2 1 0 0x00 0x4d r/w +12v in high limit 7 6 5 4 3 2 1 0 0xff 0x4e r/w remote 1 temp low limit 7 6 5 4 3 2 1 0 0x81 0x4f r/w remote 1 temp high limit 7 6 5 4 3 2 1 0 0x7f 0x50 r/w local temp low limit 7 6 5 4 3 2 1 0 0x81 0x51 r/w local temp high limit 7 6 5 4 3 2 1 0 0x7f 0x52 r/w remote 2 temp low limit 7 6 5 4 3 2 1 0 0x81 0x53 r/w remote 2 temp high limit 7 6 5 4 3 2 1 0 0x7f 0x54 r/w tach1 min low byte 7 6 5 4 3 2 1 0 0xff 0x55 r/w tach1 min high byte 15 14 13 12 11 10 9 8 0xff 0x56 r/w tach2 min low byte 7 6 5 4 3 2 1 0 0xff 0x57 r/w tach2 min high byte 15 14 13 12 11 10 9 8 0xff 0x58 r/w tach3 min low byte 7 6 5 4 3 2 1 0 0xff 0x59 r/w tach3 min high byte 15 14 13 12 11 10 9 8 0xff
adt7490 rev. 0 | page 49 of 76 addr. r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable? 0x5a r/w tach4 min low byte 7 6 5 4 3 2 1 0 0xff 0x5b r/w tach4 min high byte 15 14 13 12 11 10 9 8 0xff 0x5c r/w pwm1 config. register bhvr bhvr bhvr inv alt spin spin spin 0x62 yes 0x5d r/w pwm2 config. register bhvr bhvr bhvr inv alt spin spin spin 0x62 yes 0x5e r/w pwm3 config. register bhvr bhvr bhvr inv alt spin spin spin 0x62 yes 0x5f r/w remote 1 t range /pwm1 frequency range range range range hf/lf freq freq freq 0xc4 yes 0x60 r/w local t range /pwm2 frequency range range range range hf/lf freq freq freq 0xc4 yes 0x61 r/w remote 2 t range /pwm3 frequency range range range range hf/lf freq freq freq 0xc4 yes 0x62 r/w enhanced acoustics reg. 1 min3 min2 min1 sync en1 acou acou acou 0x00 yes 0x63 r/w enhanced acoustics reg. 2 en2 acou2 acou2 acou2 en3 acou3 acou3 acou3 0x00 yes 0x64 r/w pwm1 min duty cycle 7 6 5 4 3 2 1 0 0x80 yes 0x65 r/w pwm2 min duty cycle 7 6 5 4 3 2 1 0 0x80 yes 0x66 r/w pwm3 min duty cycle 7 6 5 4 3 2 1 0 0x80 yes 0x67 r/w remote 1 temp t min 7 6 5 4 3 2 1 0 0x5a yes 0x68 r/w local temp. t min 7 6 5 4 3 2 1 0 0x5a yes 0x69 r/w remote 2 temp t min 7 6 5 4 3 2 1 0 0x5a yes 0x6a r/w remote 1 therm temp limit 7 6 5 4 3 2 1 0 0x64 yes 0x6b r/w local therm temp. limit 7 6 5 4 3 2 1 0 0x64 yes 0x6c r/w remote 2 therm temp limit 7 6 5 4 3 2 1 0 0x64 yes 0x6d r/w remote 1 and local temp/t min hysteresis hysr1 hysr1 hysr1 hysr1 hysl hysl hysl hysl 0x44 yes 0x6e r/w remote 2 and peci temp/t min hysteresis hysr2 hysr2 hysr2 hysr2 hysp hysp hysp hysp 0x44 yes 0x6f r/w xnor tree test enable res res res res res res res xen 0x00 yes 0x70 r/w remote 1 temp offset 7 6 5 4 3 2 1 0 0x00 yes 0x71 r/w local temp offset 7 6 5 4 3 2 1 0 0x00 yes 0x72 r/w remote 2 temp offset 7 6 5 4 3 2 1 0 0x00 yes 0x73 r/w config. reg. 2 shutdown conv attn avg fan3 detect fan2detect fan1detect fanpresdt 0x00 yes 0x74 r/w interrupt mask reg. 1 ool r2t lt rit +5v in v cc v ccp +2.5v in / therm 0x00
adt7490 rev. 0 | page 50 of 76 addr. r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable? 0x75 r/w interrupt mask reg. 2 d2 fault d1 fault fan4/ therm fan3 fan2 fan1 ool +12v in / vc 0x00 0x76 r extended resolution 1 +5v in +5v in v cc v cc v ccp v ccp +2.5v in +2.5v in 0x00 0x77 r extended resolution 2 tdm2 tdm2 ltmp ltmp tdm1 tdm1 +12v in +12v in 0x00 0x78 r/w config. 3 dc4 dc 3 dc2 dc1 fast boost therm / +2.5v in alert enable 0x00 yes 0x79 r therm timer status tmr tmr tmr tm r tmr tmr tmr asrt/ tmr0 0x00 0x7a r/w therm timer limit limt limt limt limt limt limt limt limt 0x00 0x7b r/w tach pulses per revolution fan4 fan4 fan3 fan3 fan2 fan2 fan1 fan1 0x55 0x7c r/w config. register 5 r2 therm output only local therm output only r1 therm output only peci r1 therm output only res res temp offset twos compl 0x01 yes 0x7d r/w config. register 4 bpatt +12v in bpatt +5v in bpatt v ccp bpatt +2.5v in max/full on therm therm disable pin 14 func pin 14 func 0x00 yes 0x7e r test 1 do not writ e to this register 0x00 yes 0x7f r test 2 do not write to this register 0x00 yes 0x80 r/w gpio config. register gpio1 dir gpio2 dir gpio1 pol gpio2 pol gpio1 gpio2 res res 0x00 0x81 r interrupt status 4 v tt i mon peci3 peci2 peci1 res res res 0x00 0x82 r/w interrupt mask 3 ool res res res ovt comm data peci0 0x00 0x83 r/w interrupt mask 4 v tt i mon peci3 peci2 peci1 res res res 0x00 0x84 r/w v tt low limit 7 6 5 4 3 2 1 0 0x00 yes 0x85 yes r/w i mon low limit 7 6 5 4 3 2 1 0 0x00 0x86 r/w v tt high limit 7 6 5 4 3 2 1 0 0xff yes 0x87 r/w i mon high limit 7 6 5 4 3 2 1 0 0xff yes 0x88 r/w peci config. 2 #cpu #cpu dom1 dom2 dom3 res res res 0x00 yes 0x89 r test 3 do not write to this register 0x00 yes 0x8a r/w peci operating point 7 6 5 4 3 2 1 0 0xfb yes 0x8b r/w remote 1 operating point 7 6 5 4 3 2 1 0 0x64 yes 0x8c r/w local temp operating point 7 6 5 4 3 2 1 0 0x64 yes 0x8d r/w remote 2 operating point 7 6 5 4 3 2 1 0 0x64 yes 0x8e r/w dynamic t min control reg. 1 r2t lt r1t phtr2 phtl phtr1 v ccp lo cyr2 0x00 yes 0x8f r/w dynamic t min control reg. 2 cyr2 cyr2 cyl cyl cyl cyr1 cyr1 cyr1 0x00 yes 0x90 r/w dynamic t min control reg. .3 peci phtp cyp cyp cyp res res res 0x00 yes 0x94 r/w peci0 temp offset 7 6 5 4 3 2 1 0 0x00 yes 0x95 r/w peci1 temp offset 7 6 5 4 3 2 1 0 0x00 yes 0x96 r/w peci2 temp offset 7 6 5 4 3 2 1 0 0x00 yes 0x97 r/w peci3 temp offset 7 6 5 4 3 2 1 0 0x00 yes
adt7490 rev. 0 | page 51 of 76 table 25. register 0x10configuration register 6 (power-on default = 0x00) 1 bit no. mnemonic r/w 1 description [0] slow remote 1 r/w when this bit is set, fan smoothing times are multiplied 4 for remote 1 temperature channel (as defined in register 0x62). [1] slow local r/w when this bit is set, fan smoothing times are multiplied 4 for local temperature channel (as defined in register 0x63). [2] slow remote 2 r/w when this bit is set, fan smoothing times are multiplied 4 for remote 2 temperature channel (as defined in register 0x63). [3] res n/a reserved. [4] res n/a reserved. [5] res n/a reserved. [6] v ccp low r/w v ccp low = 1. when the power is supplied from 3.3 v standbyand the core voltage (v ccp ) drops below its v ccp low limit value (register 0x46), the following occurs: status bit 1 in status register 1 is set. smbalert is generated, if enabled. prochot monitoring is disabled. everything is re-enabled once v ccp increases above the v ccp low limit. when v ccp increases above the low limit: prochot monitoring is enabled. fans return to their programmed state after a spin-up cycle. [7] extraslow r/w when this bit is set, all fan smoothing times are increased by a further 39.2% 1 this register becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subseq uent attempts to writ e to this register fail. table 26. register 0x11configuration register 7 (power-on default = 0x00) bit no. mnemonic r/w 1 description [0] thermhys r/w therm hysteresis is enabled by default. setting this bit to 1 disables therm hysteresis. [1] fspd r/w when set to 1, this bit runs all fans at max imum speed as programmed in the maximum pwm duty cycle registers (0x38 to 0x3a). power-on defaul t = 0. this bit is not locked at any time. [2] vx1 r/w bios should set this bit to a 1 when the adt7490 is configured to measure current from an analog devices adopt? vrm controller and to measure the cpus core voltage. this bit allows monitoring software to display cpu watts usage. (lockable.) [3] fspdis r/w logic 1 disables fan spin-up for two tach pulses. in stead, the pwm outputs go high for the entire fan spin-up timeout selected. [4] todis r/w when this bit is set to 1, the smbus timeout feature is disabled. in this state, if at any point during an smbus transaction involving the adt7490 activity ceases for more than 35 ms, the adt7490 assumes the bus is lo cked and releases the bus. this allows the adt7490 to be used with smbus controllers th at cannot handle smbus timeouts. (lockable.) [7:5] res n/a reserved. do not write to these bits. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. an y subsequent attempts to wri te to this register fail. table 27. peci reading registers (power-on default = 0x80) register address r/w description 0x33 read-only peci0: this register reads the eight bits representative of peci client address 0x30. 0x1a read-only peci1: this register reads the eigh t bits representative of peci client address 0x31. 0x1b read-only peci2: this register reads the eigh t bits representative of peci client address 0x32. 0x1c read-only peci3: this register reads the eight bits representative of peci client address 0x33. table 28. i mon /v tt reading registers (power-on default = 0x00) register address r/w description 0x1d read-only reflects the voltage measurement at the i mon input on pin 19 (8 msbs of reading). input range of 0 v to 2.25 v. 0x1e read-only reflects the voltage measurement at the v tt input on pin 8 (8 msbs of reading). input range of 0 v to 2.25 v.
adt7490 rev. 0 | page 52 of 76 table 29. register 0x1fextended reso lution 3 (power-on default = 0x00) bit no. r/w description [3:0] read-only reserved. [5:4] read-only hold the two lsbs of the 10-bit v tt measurement. [7:6] read-only hold the two lsbs of the 10-bit i mon measurement. table 30. voltage reading registers (power-on default = 0x00) 1 register address r/w description 0x20 read-only reflects the voltage measurement at the 2.5 v in input on pin 22 (8 msbs of reading). 0x21 read-only reflects the voltage measurement 2 at the v ccp input on pin 23 (8 msbs of reading). 0x22 read-only reflects the voltage measurement 3 at the v cc input on pin 4 (8 msbs of reading). 0x23 read-only reflects the voltage measurement at the 5 v in input on pin 20 (8 msbs of reading). 0x24 read-only reflects the voltage measurement at the 12 v in input on pin 21 (8 msbs of reading). 1 if the extended resolution bits of these readings are also be ing read, the extended resolution registers (register 0x76, regis ter 0x77) must be re ad first. once the extended resolution registers have been read, the associated msb reading registers are frozen until read. both the extended res olution registers and the msb registers are frozen. 2 if v ccp low (bit 6 of 0x10) is set, v ccp can control the sleep state of the adt7490. 3 v cc (pin 4) is the suppl y voltage for the adt7490. table 31. temperature reading registers (power-on default = 0x80) 1, 2 register address r/w description 0x25 read-only remote 1 temperature reading 3, 4 (8 msb of reading). 0x26 read-only local temperature reading (8 msb of reading). 0x27 read-only remote 2 temperature reading 3, 4 (8 msb of reading). 1 if the extended resolution bits of these readings are also be ing read, the extended resolution registers (register 0x76, regist er 0x77) must be read first. once the extended resolution registers have been read, all associated msb reading registers are frozen until read. both the extended res olution registers and the msb registers are frozen. 2 these temperature readings can be in twos complement or offset 64 format; this interpretation is determined by bit 0 of config uration register 5 (0x7c). 3 in twos complement mode, a temperature re ading of ?128c (0x80) indi cates a diode fault (open or short) on that channel. 4 in offset 64 mode, a temperature reading of ?64c (0x00) indicates a diode fault (open or short) on that channel.
adt7490 rev. 0 | page 53 of 76 table 32. fan tachometer reading registers (power-on default = 0x00) 1 register address r/w description 0x28 read-only tach1 low byte. 0x29 tach1 high byte. read-only 0x2a read-only tach2 low byte. 0x2b read-only tach2 high byte. 0x2c read-only tach3 low byte. 0x2d read-only tach3 high byte. 0x2e read-only tach4 low byte. 0x2f read-only tach4 high byte. 1 these registers count the number of 11.11 s periods (based on an internal 90 khz clock) that occur between a number of consec utive fan tach pulses (default = 2). the number of tach pulses used to count can be changed using the tach pulses per revolution register (register 0x7b). this allo ws the fan speed to be accurately measured. because a valid fan tachometer reading requires that two bytes be read, the low byte must be read first. both the low and high bytes are then frozen until read. at power-on, these regist ers contain 0x0000 until the first valid fan tach measurement is read into these registers. this prevents false interrupts from occurring while the fans are spinning up. a count of 0xffff indicates that a fan is one of the following: stalled or blocked (object jammin g the fan), failed (internal c ircuitry destroyed), or not populated. (the adt7490 expects to see a fan connected to each tach. if a fan is not connected to that tach, its tach minimum high and low bytes should be set to 0xffff.) an alternate function, for example, is tach4 reconfigured as the therm pin. table 33. current pwm duty cycle registers (power-on default = 0xff) 1 register address r/w description 0x30 r/w pwm1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff). 0x31 r/w pwm2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff). 0x32 r/w pwm3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff). 1 these registers reflect the pwm duty cycle driving each fan at any given time. when in automatic fan speed control mode, the a dt7490 reports the pwm duty cycles back through these registers. the pwm duty cycle values vary according to temperature in automatic fan speed control mode. duri ng fan startup, these registers report back 0x00. in manual mode, the pwm duty cycle outputs can be set to any duty cycle value by writing to these registers. table 34. register 0x33peci0 reading register (power-on default = 0x80) register address r/w description 0x33 read-only peci0: this register reads the 8 bi ts representative of peci client address 0x30. table 35. peci limit registers register address r/w description power-on default 0x34 r/w peci low limit. 0x81 0x35 r/w peci high limit. 0x00
adt7490 rev. 0 | page 54 of 76 table 36. register 0x36peci configuratio n register 1 (power-on default = 0x00) bit no. mnemonic r/w 1 description peci smoothing interval. these bit set the duration over which smoothing is carrie d out on the peci data read. note that the peci smoothing interval is equal to the peci register update interval. [2:0] avg r/w the smoothing interval is calculated using the following formula: ) #67(# idle bit tcpu treads interval smoothing + = where: #read s is the number of readings defined below. t bit is the negotiated bit rate. 67 is the number of bits in each peci reading. #cpu is the number of cpus providing peci data (1 to 4). t idle = 14 s, the delay between consecutive reads. bit code number of peci readings 000 16 001 2048 010 4096 011 8192 100 16384 101 32768 110 65536 111 reserved [3] dom0 r/w cpu domain count information. set to 0 indicates th at cpu 1 associated with the peci0 reading has a single domain (default). set to 1 indicates that the system cpu 1 contains two domains. [4] replace r/w if this bit is set to 0, it indicates that the adt7490 is operating in standard mode. if this bit is set to 1, the remote 1 temperaute register (register 0x25) is over written by peci0 information (register 0x33) and vice versa. note that in this mode, all associated user programmable limit and fan control registers are also swapped and should be programmed in the appropriate peci or absolute temperature format. [7:5] res r reserved. 1 these registers become read-only when the configuration register 1 (0x40) lock bit is set to 1. an y subsequent attempts to wri te to these registers fail. table 37. maximum pwm duty cycle (power-on default = 0xff) 1 register address r/w 2 description 0x38 r/w maximum duty cycle for pw m1 output, default = 100% (0xff). 0x39 r/w maximum duty cycle for pw m2 output, default = 100% (0xff). 0x3a r/w maximum duty cycle for pwm3 output, default = 100% (0xff). 1 these registers set the maximum pwm duty cycle of the pwm output. 2 these registers become read-only when the configuration register 1 (0x40) lock bit is set to 1. an y subsequent attempts to wri te to these registers fail. table 38. peci t min register (power-on default = 0xe0,value = ?32) register address r/w 1 description 0x3b r/w peci t min . when the peci measurement exceeds peci t min , the appropriate fans run at pwm min and increase according to the automatic fan speed control slope. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set. any further attempts to write to this register have no effect.
adt7490 rev. 0 | page 55 of 76 table 39. register 0x3cpeci t range /enhanced acoustics register (power-on default = 0xc0) bit no. mnemonic r/w 1 description [2:0] acou r/w assuming that pwmx is associated with the peci ch annel, these bits define the maximum rate of change of the pwmx output for peci temperature-re lated changes. instead of the fan speed jumping instantaneously to its newly determined speed, it ra mps gracefully at the rate determined by these bits. this feature ultimately enhances the acoustics of the fan. the smoothing times below are based on a refresh rate of the round robin cycle. the peci data, for 0% to 100%, must be multiplied each time by cyclerobin round raterefresh peci where the peci refresh rate is defined in regist er 0x36 and the round robin cycle is typically 165 ms. when bit 7 of configuration register 6 (0x10) is 0 bit code time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec when bit 7 of configuration register 6 (0x10) is 1 bit code time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec [3] enp r/w when this bit is set to 1, smoothing is enabled on the peci channel allowing enhanced acoustics on the associated pwm output. [7:4] range r/w these bits determine the pwm duty cycle vs. the temperature range for automatic fan control. bit code temperature 0000 2c 0001 2.5c 0010 3.33c 0011 4c 0100 5c 0101 6.67c 0110 8c 0111 10c 1000 13.33c 1001 16c 1010 20c 1011 26.67c 1100 32c (default) 1101 40c 1110 53.33c 1111 80c 1 this register becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subseq uent attempts to writ e to this register fail.
adt7490 rev. 0 | page 56 of 76 table 40. t control limit registers (power-on default = 0x00) 1 register address r/w 2 description 0x3d read/write peci t control limit. 1 if any peci reading exceeds the t control limit, all pwm outputs drive their fans at 100% duty cycle. this is a fail-safe mechanism incorpor ated to cool the system in t he event of a critical overtemperature. it also ensures some level of cooling in the event that software or hardware locks up. if set to 0x80, this feature is disabled. the pwm output remains at 100% until the temperature drops below t control limit ? hysteresis. 2 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write to this register have no effect. table 41. register 0x3fversion/revisio n register (power-on default = 0x6e) bit no. mnemonic r/w description [1:0] rev read these two bits indicate the adt7490 silicon revision number. 0x00 indicates revision 0, 0x01 indicates revision 1, and so on. [2] peci read this bit is set to 1 indicating that the adt7490 supports the peci interface. [3] 4-wire read this bit is set to 1 indicating that the adt7490 ma y be configured to drive 4-wire fans using high frequency pwm. [7:4] ver read these bits indicate the version number of the device . this is set to 6, indicating that the adt7490 is part of the heceta 6 asic family. table 42. register 0x40configuration register 1 (power-on default = 0x04) bit no. mnemonic r/w 1 description [0] strt 2,3 r/w logic 1 enables monitoring and pwm control outputs based on the limit settings programmed. logic 0 disables monitoring and pwm control is based on the default power-up limit settings. note that the limit values progra mmed are preserved even if a logic 0 is written to this bit and the default settings are enabled. this bit does not become locked once bit 1 (lock bit) has been set. [1] lock write once logic 1 locks all limit values to their current settings. once this bit is set, all lockable registers become read-only and cannot be modified unti l the adt7490 is powered down and powered up again. this prevents rogue programs such as viru ses from modifying critical system limit settings. (lockable.) [2] rdy read-only this bit is set to 1 by the adt7490 to indicate that the device is fully powered-up and ready to begin system monitoring. [3] fan boost r/w when this bit is set to logic 1, all pwm o utputs go to 100% regardless of other fan speed configurations and automatic fan speed control setti ngs. when this bit is set to 0, the fan speed control returns to the fan speed setting calculated by the preprogrammed fan speed control settings. this bit remains writable after the lock bit is set. [4] peci monitor r/w set this bit to logic 1 to enable cpu thermal monitoring via peci interface. this bit becomes read- only when the lock bit is set. [5] therm in manual r/w when this bit is set to logic 1, therm is enabled so that the fans go to 100% duty cycle on a therm or t control assertion overriding any other fan setting, even when the pwms are configured for manual mode, or disabled. this bit become s read-only when the lock bit is set. [7:6] res read reserved. 1 this register becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subseq uent attempts to writ e to this register fail. 2 bit 0 (strt) of configuration register 1 (0x40) remains writable after the lock bit is set. 3 when monitoring (strt) is di sabled, pwm outputs always go to 100% for thermal protection.
adt7490 rev. 0 | page 57 of 76 table 43. register 0x41interrupt status register 1 (power-on default = 0x00) bit no. mnemonic r/w description [0] +2.5v in / therm read-only +2.5v in = 1 indicates that the 2.5 v in high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. if pin 22 is configured as therm , this bit is asserted when the timer limit has been exceeded. [1] v ccp read-only v ccp = 1 indicates that the v ccp high or low limit has been exceeded. this bit is cleared on a read of the status register only if th e error condition has subsided. [2] v cc read-only v cc = 1 indicates that the v cc high or low limit has been exceeded. this bit is cleared on a read of the status register only if th e error condition has subsided. [3] +5v in read-only +5v in = 1 indicates that the 5 v in high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [4] r1t read-only r1t = 1 indicates that the remote 1 low or high temperature has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [5] lt read-only lt = 1 indicates that the local low or high temperature has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [6] r2t read-only r2t = 1 indicates that the remote 2 low or high temperature has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [7] ool read-only ool = 1 indicates that an out-of-limit event has been latched in status register 2 (0x42). this bit is a logical or of all status bits in status register 2. software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by status register 2 are out-of-limit, which eliminates the need to read status register 2 during every interrupt or polling cycle. table 44. register 0x42interrupt status register 2 (power-on default = 0x00) bit no. mnemonic r/w description [0] +12v in read-only +12v in = 1 indicates that the 12 v in high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [1] ool read-only ool = 1 indicates that an out-of-limit event has been latched in status register 3 (0x43). this bit is a logical or of all status bits in status register 3. software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by status register 3 are out-of-limit, which eliminates the need to read status register 3 during every interrupt or polling cycle. [2] fan1 read-only fan1 = 1 indicates that fan 1 has dropped below minimum speed or has stalled. this bit is not set when the pwm1 output is off. [3] fan2 read-only fan2 = 1 indicates that fan 2 has dropped below minimum speed or has stalled. this bit is not set when the pwm2 output is off. [4] fan3 read-only fan3 = 1 indicates that fan 3 has dropped below minimum speed or has stalled. this bit is not set when the pwm3 output is off. [5] fan4/ therm read-only when pin 14 is programmed as a tach4 input, fan4 = 1 indicates that fan 4 has dropped below minimum speed or has stalled. this bit is not set when the pwm3 output is off. read-only if pin 14 is configured as the therm timer input for therm monitoring, this bit is set when the therm assertion time exceeds the limit programmed in the therm timer limit register (register 0x7a). [6] d1 fault read-only d1 fault = 1 indicates either an open or short circuit on the thermal diode 1 inputs. [7] d2 fault read-only d2 fault = 1 indicates either an open or short circuit on the thermal diode 2 inputs.
adt7490 rev. 0 | page 58 of 76 table 45. register 0x43interrupt status register 3 (power-on default = 0x00) bit no. mnemonic r/w description [0] peci0 read-only a logic 1 indicates that the peci high or low limi t has been exceeded by the peci value from peci client address 0x30. this bit is cleared on a read of the status register only if the error condition has subsided. [1] data read-only a logic 1 indicates that valid peci data cannot be obtained for the processor and a specified error code has been recorded. [2] comm read-only a logic 1 indicates that there is a communications error (for example, invalid fcs) on the peci interface. [3] ovt read-only ovt = 1 indicates that one of the therm overtemperature limits has been exceeded. this bit is cleared on a read of the status register when the temperature drops below therm ? t hyst . [6:4] res read-only reserved. [7] ool read-only ool = 1 indicates that an out-of-limit event has been latched in status register 4 (0x81). this bit is a logical or of all status bits in status register 4. software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by status register 4 are out-of-limit, which eliminates the need to read status register 4 during every interrupt or polling cycle. table 46. voltage limit registers 1 register address r/w description 2 power-on default 0x44 r/w +2.5v in low limit. 0x00 0x45 r/w +2.5v in high limit. 0xff 0x46 r/w v ccp low limit. 0x00 0x47 r/w v ccp high limit. 0xff 0x48 r/w v cc low limit. 0x00 0x49 r/w v cc high limit. 0xff 0x4a r/w +5v in low limit. 0x00 0x4b r/w +5v in high limit. 0xff 0x4c r/w +12v in low limit. 0x00 0x4d r/w +12v in high limit. 0xff 1 setting the configuration register 1 (0x40) lock bit has no effect on these registers. 2 high limits: an interrupt is ge nerated when a value exceeds its high limit (> comparison). low limits: an interrupt is generat ed when a value is equal to or below its low limit ( comparison). table 47. temperature limit registers 1 register address r/w description 2 power-on default 0x4e r/w remote 1 temperature low limit. 0x81 0x4f r/w remote 1 temperature high limit. 0x7f 0x50 r/w local temperature low limit. 0x81 0x51 r/w local temperature high limit. 0x7f 0x52 r/w remote 2 temperature low limit. 0x81 0x53 r/w remote 2 temperature high limit. 0x7f 1 exceeding any of these temperat ure limits by 1c causes the appropriate status bit to be set in the interrupt status register. setting the configuration register 1 lock (0x40) bit has no effect on these registers. 2 high limits: an interrupt is ge nerated when a value exceeds its high limit (> comparison). low limits: an interrupt is generat ed when a value is equal to or below its low limit ( comparison).
adt7490 rev. 0 | page 59 of 76 table 48. fan tachometer limit registers 1 register address r/w description power-on default 0x54 r/w tach1 minimum low byte. 0xff 0x55 r/w tach1 minimum high byte/single-channel adc channel select. 0xff 0x56 r/w tach2 minimum low byte. 0xff 0x57 r/w tach2 minimum high byte. 0xff 0x58 r/w tach3 minimum low byte. 0xff 0x59 r/w tach3 minimum high byte. 0xff 0x5a r/w tach4 minimum low byte. 0xff 0x5b r/w tach4 minimum high byte. 0xff 1 exceeding any of the tach limit registers by 1 indicates that the fan is running too slowly or has stalled. the appropriate sta tus bit is set in inte rrupt status register 2 (0x42) to indicate the fan failure. setting the configuration register 1 (0x40) lock bit has no effect on these registers. table 49. register 0x55tach1 minimum high byte (power-on default = 0xff) bits mnemonic r/w description [3:0] reserved read-only when bit 6 of configuration 2 register (0x73) is se t (single-channel adc mode), these bits are reserved. otherwise, these bits represent bits [3:0] of the tach1 minimum high byte. [7:4] scadc r/w when bit 6 of configuration 2 register (0x73) is se t (single-channel adc mode), these bits are used to select the only channel from which the adc will take measurements. otherwise, these bits represent bits [7:4] of the tach1 minimum high byte. bit code single-channel select 0000 +2.5v in 0001 v ccp 0010 v cc 0011 +5v in 0100 +12v in 0101 remote 1 temperature 0110 local temperature 0111 remote 2 temperature 1000 v tt 1001 i mon
adt7490 rev. 0 | page 60 of 76 table 50. pwm configuration registers register address r/w 1 description power-on default 0x5c r/w pwm1 configuration. 0x62 0x5d r/w pwm2 configuration. 0x62 0x5e r/w pwm3 configuration. 0x62 1 these registers become read-only when the configuration register 1 (0x40) lock bit is set to 1. an y subsequent attempts to wri te to these registers fail. table 51. register 0x5c, register 0x 5d, and register 0x5epwm1, pwm2, and pwm3 configuration registers (power-on default = 0x62) bit no. mnemonic r/w 1 description [2:0] spin r/w these bits control the start-up timeout for pwmx. the pwm output stays high until two valid tach rising edges are seen from the fan. if there is not a valid tach signal during the fan tach measurement directly after the fan start-up timeout period, the tach measurement reads 0xffff and status re gister 2 reflects the fan fault. if the tach minimum high and low bytes contain 0xffff or 0x0000, then the status register 2 bit is not set, even if the fan has not started. bit code start-up timeout 000 no start-up timeout 001 100 ms 010 250 ms (default) 011 400 ms 100 667 ms 101 1 sec 110 2 sec 111 4 sec [3] alt r/w use alternative behavior setting options in bits[7:5] below for pwmx by setting this bit to 1. default =0. [4] inv r/w this bit inverts the pwm output. the default is 0, which corresponds to a logic high output for 100% duty cycle. setting this bit to 1 inverts the pwm output, so 100% duty cycle corresponds to a logic low output. [7:5] bhvr 2 r/w these bits assign each fan to a particular temperature sensor for localized cooling. setting bit 3 to logic 1 in this register chooses whether the default of alternative behavior option is selected. default behavior bits alternative behavior bits 2 000 = remote 1 temperature controls pwmx (automatic fan control mode). 000 = peci0 reading controls pwmx (automatic fan control mode). 001 = local temperature controls pwmx (automatic fan control mode). 001 = peci1 reading controls pwmx (automatic fan control mode). 010 = remote 2 temperature controls pwmx (automatic fan control mode). 010 = peci2 reading controls pwmx (automatic fan control mode). 011 = pwmx runs full speed (default). 011 = peci3 reading controls pwmx (automatic fan control mode). 100 = pwmx disabled. 100 = reserved. if selected, fans run at 100% duty cycle. 101 = fastest speed calculated by local and remote 2 temperature controls pwmx. 101 = fastest of all 4 peci channels. fastest speed calculated by all 4 peci readings. 110 = fastest speed calculated by all three temperature channel controls pwmx. 110 = reserved. if selected, fans run at 100% duty cycle. 111 = manual mode. pwm duty cycle registers (register 0x30 to register 0x32) become writable. 111 = fastest speed calculated by all of the thermal zones (local, remote 1, remote 2 and peci temperatures). 1 this register becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subseq uent attempts to writ e to this register fail. 2 when replace mode is selected, (register 0x36, bit 4 set to 1) pwm1 is automatically configured for the alternative behavior s etting. register 0x36 bits [7:5] should be set to 000 only.
adt7490 rev. 0 | page 61 of 76 table 52. temperature t range /pwm frequency registers register address r/w 1 description power-on default 0x5f r/w remote 1 t range /pwm1 frequency. 0xc4 0x60 r/w local temperature t range /pwm2 frequency. 0xc4 0x61 r/w remote 2 t range /pwm3 frequency. 0xc4 1 these registers become read-only when the configuration register 1 (0x40) lock bit is set. any fur ther attempts to write to th ese registers have no effect. table 53. register 0x5f, register 0x60, and register 0x61remote 1 t range /pwm1 frequency, local temperature t range /pwm2 frequency, and remote 2 t range /pwm3 frequency (power-on default = 0xc4) bit no. mnemonic r/w 1 description [2:0] freq r/w these bits control th e pwmx frequency (only apply when pwm channel is in low frequency mode). bit code frequency 000 11.0 hz 001 14.7 hz 010 22.1 hz 011 29.4 hz 100 35.3 hz (default) 101 44.1 hz 110 58.8 hz 111 88.2 hz [3] hf/lf r/w hf/lf = 1, high freq uency pwm mode is enabled for pwmx. hf/lf = 0, low frequency pwm mode is enabled for pwmx. [7:4] range r/w these bits determine the pwm duty cycl e vs. the temperature range for automatic fan control. bit code temperature 0000 2c 0001 2.5c 0010 3.33c 0011 4c 0100 5c 0101 6.67c 0110 8c 0111 10c 1000 13.33c 1001 16c 1010 20c 1011 26.67c 1100 32c (default) 1101 40c 1110 53.33c 1111 80c 1 this register becomes read-only when the configuration register 1 (0x40) lock bit is set. any further attempts to write to thi s register have no effect.
adt7490 rev. 0 | page 62 of 76 table 54. register 0x62enhanced acoustic s register 1 (power-on default = 0x00) bit no. mnemonic r/w 1 description [2:0] acou 2 r/w assuming that pwmx is associated with the remote 1 temperature channel, these bits define the maximum rate of change of the pw mx output for remote 1 tempera ture-related changes. instead of the fan speed jumping instantaneously to its newly de termined speed, it ramps gracefully at the rate determined by these bits. this feature ultimately enhances the acoustics of the fan. when bit 7 of configuration register 6 (0x10) is 0 bit code time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec when bit 7 of configuration register 6 (0x10) is 1 bit code time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec [3] en1 r/w when this bit is 1, smoothing is enabled on remote 1 temperature channel. [4] sync r/w sync = 1 synchronizes fan speed measurements on tach2, tach3, and tach4 to pwm3. this allows up to three fans to be driven from pwm3 output and their speeds to be measured. sync = 0 synchronizes only tach3 and tach4 to pwm3 output. [5] min1 r/w when the adt7490 is in automatic fan control mo de, this bit defines whether pwm1 is off (0% duty cycle) or at pwm1 minimum duty cycle when the controlling temperature is below its t min ? hysteresis value. 0 = 0% duty cycle below t min C hysteresis. 1 = pwm1 minimum duty cycle below t min C hysteresis. [6] min2 r/w when the adt7490 is in automatic fan speed contro l mode, this bit defines whether pwm2 is off (0% duty cycle) or at pwm2 minimum duty cycle when the controlling temperature is below its t min ? hysteresis value. 0 = 0% duty cycle below t min C hysteresis. 1 = pwm2 minimum duty cycle below t min C hysteresis. [7] min3 r/w when the adt7490 is in automatic fan speed contro l mode, this bit defines whether pwm3 is off (0% duty cycle) or at pwm3 minimum duty cycle when the controlling temperature is below its t min C hysteresis value. 0 = 0% duty cycle below t min C hysteresis. 1 = pwm3 minimum duty cycle below t min C hysteresis. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write to this register have no effect. 2 setting the relevant bit of configuration register 6 (0x10, bits [2:0]) furthe r decreases these ramp rates by a factor of 4.
adt7490 rev. 0 | page 63 of 76 table 55. register 0x63enhanced acoustic s register 2 (power-on default = 0x00) bit no. mnemonic r/w 1 description [2:0] acou3 r/w assuming that pwmx is associated with the loca l temperature channel, these bits define the maximum rate of change of the pw mx output for local temperature- related changes. instead of the fan speed jumping instantaneously to its newly dete rmined speed, it ramps gracefully at the rate determined by these bits. this feature ultimately enhances the acoustics of the fan. when bit 7 of configuration register 6 (0x10) is 0 bit code time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec when bit 7 of configuration register 6 (0x10) is 1 bit code time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec [3] en3 r/w when this bit is 1, smoothing is enabled on the local temperature channel. [6:4] acou2 r/w assuming that pwmx is associated with the remote 2 temperature channel, these bits define the maximum rate of change of the pw mx output for remote 2 tempera ture related changes. instead of the fan speed jumping instantaneously to its newly de termined speed, it ramps gracefully at the rate determined by these bits. this feature ultimately enhances the acoustics of the fan. when bit 7 of configuration register 6 (0x10) is 0 time slot increase time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec when bit 7 of configuration register 6 (0x10) is 1 time slot increase time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec [7] en2 r/w when this bit is 1, smoothing is enabled on the remote 2 temperature channel. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write to this register have no effect.
adt7490 rev. 0 | page 64 of 76 table 56. pwm minimum duty cycle registers register address r/w 1 description power-on default 0x64 r/w pwm1 minimum duty cycl e. 0x80 (50% duty cycle) 0x65 r/w pwm2 minimum duty cycle. 0x80 (50% duty cycle) 0x66 r/w pwm3 minimum duty cycle. 0x80 (50% duty cycle) 1 these registers become read-only when the adt7490 is in automatic fan control mode. table 57. register 0x64, register 0x65, and register 0x66pwm 1, pwm2, and pwm3 min duty cycles (power-on default = 0x80) bit no. mnemonic r/w 1 description [7:0] pwm duty cycle r/w these bits define the pwm min duty cycle for pwmx. 0x00 = 0% duty cycle (fan off ). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xff = 100% duty cycle (fan full speed). 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect.. table 58. t min registers 1 register address r/w 2 description power-on default 0x67 r/w remote 1 temperature t min . 0x5a (90c) 0x68 r/w local temperature t min . 0x5a (90c) 0x69 r/w remote 2 temperature t min . 0x5a (90c) 1 these are the t min registers for each temperature channel. when the temperature measured exceeds t min , the appropriate fan runs at minimum speed and increases with temperature according to t range . 2 these registers become read-only when the configuration re gister 1 (0x40) lock bit is set. any further attempts to write to the se registers have no effect. table 59. therm limit registers 1 register address r/w 2 description power-on default 0x6a r/w remote 1 therm temperature limit. 0x64 (100c) 0x6b r/w local therm temperature limit. 0x64 (100c) 0x6c r/w remote 2 therm temperature limit. 0x64 (100c) 1 if any temperature me asured exceeds its therm limit, all pwm outputs drive their fans at 100% duty cycle. this is a fail-safe mechanism incorporated to cool the system in the event of a critical over temperature. it also ensures some level of cooling in the event that software or hardwar e locks up. if set to 0x80, this feature is disabled. the pwm output remains at 100% until the temperature drops below therm limit ? hysteresis. if the therm pin is programmed as an output, exceeding these limits by 0.25c can cause the therm pin to assert low as an output. 2 these registers become read-only wh en the configuration register 1 (0x40) lock bit is set to 1. any further attempts to write t o these registers have no effect.
adt7490 rev. 0 | page 65 of 76 table 60. temperature/t min hysteresis registers register address r/w 1 description power-on default 0x6d r/w remote 1 and local temperature/t min hysteresis . 0x44 0x6e r/w peci and remote 2 temperature/t min hysteresis. 0x44 1 these registers become read-only when the configuration register 1(0x40) lock bit is set to 1. any further attempts to write t o these registers have no effect. table 61. register 0x6dremote 1 and local temp/t min hysteresis (power-on default = 0x44) bit no. 1 mnemonic r/w 2 description [3:0] hysl r/w local temperature hysteresis. 0c to 15c of hysteresis can be applied to the local temperature afc control loops. [7:4] hysr1 r/w remote 1 temperature hysteresis. 0c to 15c of hyst eresis can be applied to the remote 1 temperature afc control loops. 1 each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. once the temperatu re for that channel falls below its t min value, the fan remains running at pwm min duty cycle until the temperature = t min ? hysteresis. up to 15c of hysteresis can be assigned to any temperature channel. the hysteresis value chosen also applies to that temperature channel if its therm limit is exceeded. the pwm output being controlled goes to 100%, if the therm limit is exceeded and remains at 100 % until the temperature drops below therm ? hysteresis. for acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4c. setting the hysteresis valu e lower than 4c causes the fan to switch on and off regularl y when the temperature is close to t min . 2 these registers become read-only when the configuration register 1 lock bit is set to 1. any further attempts to write to thes e registers have no effect. table 62. register 0x6eremote 2 and peci te mp/tmin hysteresis (power-on default = 0x44) bit no. 1 mnemonic r/w 2 description [3:0] hysp r/w peci temperature hysteresis. 0c to 15c of hysteresis can be applied to the peci afc control loops. [7:4] hysr2 r/w remote 2 temperature hysteresis. 0c to 15c of hy steresis can be applied to the local temperature afc control loops. 1 each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. once the temperatu re for that channel falls below its t min value, the fan remains running at pwm min duty cycle until the temperature = t min ? hysteresis. up to 15c of hysteresis can be assigned to any temperature channel. the hysteresis value chosen also applies to that temperature channel, if its therm limit is exceeded. the pwm output being controlled goes to 100%, if the therm limit is exceeded and remains at 100 % until the temperature drops below therm ? hysteresis. for acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4c. setting the hysteresis valu e lower than 4c causes the fan to switch on and off regularl y when the temperature is close to t min . 2 these registers become read-only when the configuration register 1 (0x40) lock bit is set to 1. an y further attempts to write to these registers have no effect. table 63. register 0x6fxnor tree test enable (power-on default = 0x00) bit no. mnemonic r/w 1 description [0] xen r/w if the xen bit is set to 1, the device enters the xnor tree test mode. clearing the bit removes the device from the xnor tree test mode. [7:1] res r/w unused/reserved. do not write to these bits. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect. table 64. register 0x70remote 1 temper ature offset (power-on default = 0x00) bit no. r/w 1 description [7:0] r/w allows a temperature offset to be automatically applie d to the remote 1 temperature channel measurement. bit 1 of configuration register 5 (0x7c) determines the range and resolution of this register. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect.
adt7490 rev. 0 | page 66 of 76 table 65. register 0x71local temperat ure offset (power-on default = 0x00) bit no. r/w 1 description [7:0] r/w allows a temperature offset to be automatically appl ied to the local temperature measurement. bit 1 of configuration register 5 (0x7c) determines the range and resolution of this register. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect. table 66. register 0x72remote 2 temperature offset (power-on default = 0x00) bit no. r/w 1 description [7:0] r/w allows a temperature offset to be automatically applie d to the remote 2 temperature channel measurement. bit 1 of configuration register 5 (0x7c) determines the range and resolution of this register. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect. table 67. register 0x73configuration register 2 (power-on default = 0x00) bit no. mnemonic r/w 1 description 0 fanpresdt r/w when fanpresdt = 1, the state of bits [3:1] of this register reflects the presence of a 4-wire fan on the appropriate tach channel. 1 fan1detect read fan1detect = 1 indicates that a 4-wire fan is connected to the pwm1 input. 2 fan2detect read fan2detect = 1 indicates that a 4-wire fan is connected to the pwm2 input. 3 fan3detect read fan3detect = 1 indicates that a 4-wire fan is connected to the pwm3 input. 4 avg r/w avg = 1 indicates that averaging on the temperature and voltage measurements is turned off. this allows measurements on each channel to be made much faster (x16). 5 attn r/w attn = 1 indicates that the adt7490 removes the attenuators from the +2.5v in , v ccp , +5v in , and +12v in inputs. these inputs can be used for other functions such as connecting up external sensors. it is also possible to remove attenuator s from individual channels using bits [7:4] of configuration register 4 (0x7d). 6 conv r/w conv = 1 indicates that the adt7490 is put into a single-channel adc conversion mode. in this mode, the adt7490 can be made to read cont inuously from one input only, for example, remote 1 temperature. the appropriate adc channel is selected by writing to bits [7:4] of tach1 minimum high byte register (0x55). when conv = 1, bits [7:4], register 0x55 bit code adc channel selected 0000 +2.5v in 0001 v ccp 0010 v cc 0011 +5v in 0100 +12v in 0101 remote 1 temperature 0110 local temperature 0111 remote 2 temperature 1000 v tt 1001 i mon 7 shutdown r/w when the shut down bit is set to 1, the ad t7490 goes into shutdown mode. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect.
adt7490 rev. 0 | page 67 of 76 table 68. register 0x74interrupt mask register 1 (power-on default = 0x00) bit no. mnemonic r/w description [0] +2.5v in / therm r/w +2.5v in /therm = 1 masks smbalert for out-of-limit conditions on the +2.5v in /therm timer channel. [1] v ccp r/w v ccp = 1 masks smbalert for out-of-limit conditions on the v ccp channel. [2] v cc r/w v cc = 1 masks smbalert for out-of-limit conditions on the v cc channel. [3] +5v in r/w +5v in = 1 masks smbalert for out-of-limit conditions on the +5v in channel. [4] r1t r/w r1t = 1 masks smbalert for out-of-limit conditions on the remote 1 temperature channel. [5] lt r/w lt = 1 masks smbalert for out-of-limit conditions on the local temperature channel. [6] r2t r/w r2t = 1 masks smbalert for out-of-limit conditions on the remote 2 temperature channel. [7] ool r/w ool = 1 masks smbalert assertions when the ool status bit is set. note that the ool mask bit is in dependent of the individual mask bits associated with interrupt status 2 register. therefore, if the intention is to mask smbalert assertions for any of the interrupt status 2 register bits, ool must also be masked. table 69. register 0x75interrupt mask register 2 (power-on default = 0x00) bit no. mnemonic r/w description [0] +12v in r/w when pin 21 is configured as a +12v in input, +12v in = 1 masks smbalert for out-of-limit conditions on the +12v in channel. [1] ool r/w ool = 1 masks smbalert assertions when the ool status bit is set. note that the ool mask bit is inde pendent of the individual mask bi ts in interrupt mask 3 register (0x82). therefore, if the intention is to mask smbalert assertions for any of the status register 4 bits, ool must also be masked. [2] fan1 r/w fan1 = 1 masks smbalert for a fan 1 fault. [3] fan2 r/w fan2 = 1 masks smbalert for a fan 2 fault. [4] fan3 r/w fan3 = 1 masks smbalert for a fan 3 fault. [5] f4p r/w if pin 14 is configured as tach4, f4p = 1 masks smbalert for a fan 4 fault. if pin 14 is configured as therm , f4p = 1 masks smbalert for an exceeded therm timer limit. [6] d1 r/w d1 = 1 masks smbalert for a diode open or short on a remote 1 channel. [7] d2 r/w d2 = 1 masks smbalert for a diode open or short on a remote 2 channel. table 70. register 0x76extended resolution register 1 (power-on default = 0x00) 1 bit no. mnemonic r/w description [1:0] +2.5v in read-only +2.5v in lsbs. holds the 2 lsbs of the 10-bit +2.5v in measurement. [3:2] v ccp read-only v ccp lsbs. holds the 2 lsbs of the 10-bit v ccp measurement. [5:4] v cc read-only v cc lsbs. holds the 2 lsbs of the 10-bit v cc measurement. [7:6] +5v in read-only +5v in lsbs. holds the 2 lsbs of the 10-bit +5v in measurement. 1 if this register is read, this regist er and the registers holding the msb of each reading are frozen until read. table 71. register 0x77extended resolution register 2 (power-on default = 0x00) 1 bit name r/w description [1:0] +12v in read-only +12v in lsbs. holds the 2 lsbs of the 10-bit +12v in measurement. [3:2] tdm1 read-only remote 1 temperature lsbs. holds th e 2 lsbs of the 10-bit remote 1 temperature measurement. [5:4] ltmp read-only local temperature lsbs. holds th e 2 lsbs of the 10-bit local temperature measurement. [7:6] tdm2 read-only remote 2 temperature lsbs. holds the 2 lsbs of the 10-bit remote 2 temperature measurement. 1 if this register is read, this regist er and the registers holding the msb of each reading are frozen until read.
adt7490 rev. 0 | page 68 of 76 table 72. register 0x78configuration register 3 (power-on default = 0x00) bit no. mnemonic r/w 1 description [0] alert enable r/w alert = 1, pin 10 (pwm2/ smbalert ) is configured as an smbalert interrupt output to indicate out-of-limit error conditions. alert = 0, pin 10 (pwm2/ smbalert ) is configured as the pwm2 output. [1] therm / +2.5v in r/w therm = 1 enables therm functionality on pin 22 and pin 14, if pin 14 is configured as therm , determined by bit 0 and bit 1 (pin 14 func) of configuration register 4 (0x7d). when therm is asserted, if the fans are running and the boost bit is set, then the fans run at full speed. alterna- tively, therm can be programmed so that a timer is triggered to time how long therm has been asserted. therm = 0 enables +2.5v in measurement on pin 22 and disables therm . if bits [5:7] of configuration register 5 (0x7c) are set, therm is bidirectional. if they are 0, therm is a timer input only. pin 14 func (0x7d) therm /+2.5v in (0x78) pin 22 pin 14 00 0 +2.5v in tach4 01 0 +2.5v in tach4 10 0 +2.5v in smbalert 11 0 +2.5v in n/a 00 1 therm tach4 01 1 +2.5v in therm 10 1 therm smbalert 11 1 therm n/a [2] boost r/w when therm is an input and boost = 1, assertion of therm causes all fans to run at the maximum programmed duty cycle for fail-safe cooling. [3] fast r/w fast = 1 enables fast tach measurements on al l channels. this increases the tach measurement rate from once per second to once every 250 ms (4). [4] dc1 r/w dc1 = 1 enables tach measurements to be continuo usly made on tach1. fans must be driven by dc. setting this bit prevents pulse stretching be cause it is not required for dc-driven motors. [5] dc2 r/w dc2 = 1 enables tach measurements to be continuo usly made on tach2. fans must be driven by dc. setting this bit prevents pulse stretching be cause it is not required for dc-driven motors. [6] dc3 r/w dc3 = 1 enables tach measurements to be continuo usly made on tach3. fans must be driven by dc. setting this bit prevents pulse stretching be cause it is not required for dc-driven motors. [7] dc4 r/w dc4 = 1 enables tach measurements to be continuo usly made on tach4. fans must be driven by dc. setting this bit prevents pulse stretching be cause it is not required for dc-driven motors. 1 bits [3:0] of this register become read-o nly when the configuration regi ster 1 lock (0x40) bit is set to 1. any further attemp ts to write to bits [3:0] have no effect. table 73. register 0x79 therm timer status register (power-on default = 0x00) bit no. mnemonic r/w description [0] asrt/ tmr0 r/w this bit is set high on the assertion of the therm input and is cleared on read. if the therm assertion time exceeds 45.52 ms, this bit is set and becomes the lsb of the 8-bit tmr reading. this allows therm assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of 22.76 ms. [7:1] tmr r/w times how long therm input is asserted. these seven bits read zero until the therm assertion time exceeds 45.52 ms. table 74. register 0x7a therm timer limit register (power-on default = 0x00) bit no. mnemonic r/w description [7:0] limt r/w sets maximum therm assertion length allowed before an interr upt is generated. this is an 8-bit limit with a resolution of 22.76 ms allowing therm assertion limits of 45.52 ms to 5.82 s to be programmed. if the therm assertion time exceeds this limit, bit 5 (fan4/ therm ) of interrupt status 2 register (0x42) is set. if the limit value is 0x00, an interrup t is generated immediately on the assertion of the therm input. if therm is configured as an output, the therm timer limit should be set to 0xff to avoid unwanted alerts from being generated.
adt7490 rev. 0 | page 69 of 76 table 75. register 0x7btach pulses per revo lution register (power-on default = 0x55) bit no. mnemonic r/w description [1:0] fan1 r/w sets number of pulses to be counted when measur ing fan 1 speed. can be used to determine fan pulses per revolution for unknown fan type. bit code pulses counted 00 1 01 2 (default) 10 3 11 4 [3:2] fan2 r/w sets number of pulses to be counted when measur ing fan 2 speed. can be used to determine fan pulses per revolution for unknown fan type. bit code pulses counted 00 1 01 2 (default) 10 3 11 4 [5:4] fan3 r/w sets number of pulses to be counted when measur ing fan 3 speed. can be used to determine fan pulses per revolution for unknown fan type. bit code pulses counted 00 1 01 2 (default) 10 3 11 4 [7:6] fan4 r/w sets number of pulses to be counted when measur ing fan 4 speed. can be used to determine fan pulses per revolution for unknown fan type. bit code pulses counted 00 1 01 2 (default) 10 3 11 4 table 76. register 0x7cconfiguration register 5 (power-on default = 0x01) bit no. mnemonic r/w 1 description [0] twos compl r/w twos compl = 1 sets the temperatur e range to the twos complement temperature range. twos compl = 0 changes the temperature range to the offset 64 temperature range. when this bit is changed, the adt7490 interprets all relevant temperature register values as defined by this bit. [1] temp offset r/w temp offset = 0 sets offset range to ?63c to +64c with 0.5c resolution. temp offset = 1 sets offset range to ?63c to +127c with 1c resolution. these settings apply to register 0x70, register 0x71, and register 0x72 (remote 1, internal, and remote 2 temperature offset registers. note that peci offset is always 1c resolution). [2] res r/w reserved. [3] res r/w reserved. [4] peci r1 therm output only r/w peci r1 = 1 enables therm assertions when the peci tempera ture read is higher than the peci t control limit and the therm pin is bidirectional. if therm is configured as an output, the therm timer limit register (0x7a) should be set to 0xff to avoid unwanted alerts from being generated. peci r1 = 0 indicates that the therm pin is configured as a timer input only. can also be disabled by writing one of the following values to the peci t control limit register (0x3d): writing ?64c in offset 64 mode. writing ?128c in twos complement mode.
adt7490 rev. 0 | page 70 of 76 bit no. mnemonic r/w 1 description [5] r1 therm output only r/w r1 = 1 enables therm assertions when the remote 1 temperature read is higher than the remote 1 therm limit and the therm pin is bidirectional. if therm is configured as an output, the therm timer limit (register 0x7a) should be set to 0xff to avoid unwanted alerts from being generated. r1 = 0 indicates that the therm pin is configured as a timer input only. can also be disabled by writing one of the following values to the remote 1 therm temp limit register (0x6a): writing ?64c in offset 64 mode. writing ?128c in twos complement mode. [6] local therm output only r/w r1 = 1 enables therm assertions when the local temperature read is higher than the local therm limit and the therm pin is bidirectional. if therm is configured as an output, the therm timer limit (register 0x7a) should be set to 0xff to avoid unwanted alerts from being generated. r1 = 0 indicates that the therm pin is configured as a timer input only. can also be disabled by writing one of the below values to the local therm limit register (0x6b): writing ?64c in offset 64 mode. writing ?128c in twos complement mode. [7] r2 therm output only r/w r1 = 1 enables therm assertions when the remote 2 temperature read is higher than the remote 2 therm limit and the therm pin is bidirectional. if therm is configured as an output the therm timer limit (register 0x7a) should be set to 0xff to avoid unwanted alerts from being generated. r1 = 0 indicates that the therm pin is configured as a timer inp ut only. c an also be disabled by writing one of the below values to the remote 2 therm temp limit register (0x6c): writing ?64c in offset 64 mode. writing ?128c in twos complement mode. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect. table 77. register 0x7dconfiguration register 4 (power-on default = 0x00) bit no. mnemonic r/w 1 description [1:0] pin 14 func r/w these bits set the functionality of pin 14. 00 = tach4 (default) 01 = therm 10 = smbalert 11 = reserved [2] therm disable r/w therm disable = 0 enables therm overtemperature output assuming therm is correctly configured (0x78, 0x7c, and 0x7d). therm disable = 1 disables therm overtemperature output on all channels. therm can also be disabled on any channel by: writing ?64c to the appropriate therm temperature limit in offset 64 mode. writing ?128c to the appropriate therm temperature limit in twos complement mode. [3] max/full on r/w max/full on therm = 0 indicates that fans go to 100% when therm temperature limit is exceeded. therm max/full on therm = 1 indicates that fans go to ma ximum speed (0x38, 0x39, 0x3a) when therm temperature limit is exceeded. [4] bpatt +2.5v in r/w bypass +2.5v in attenuator. when set, the measurement scale for this channel changes from 0 v (0x00) to 2.25 v (0xff). [5] bpatt v ccp r/w bypass v ccp attenuator. when set, the measurement scale for this channel changes from 0 v (0x00) to 2.25 v (0xff). [6] bpatt +5v in r/w bypass +5v in attenuator. when set, the measurement scal e for this channel changes from 0 v (0x00) to 2.25 v (0xff). [7] bpatt +12v in r/w bypass +12v in attenuator. when set, the measurement scale for this channel changes from 0 v (0x00) to 2.25 v (0xff). 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect.
adt7490 rev. 0 | page 71 of 76 table 78. register 0x7emanufacturers te st register 1 (power-on default = 0x00) bit no. mnemonic r/w description [7:0] reserved read-only manufacturers test register. these bits are reserved for manufacturers test purposes and should not be written to under normal operation. table 79. register 0x7fmanufacturers te st register 2 (power-on default = 0x00) bit no. mnemonic r/w description [7:0] reserved read-only manufacturers test register. these bits are reserved for manufacturers test purposes and should not be written to under normal operation. table 80. register 0x80gpio configurat ion register (power-on default = 0x00) bit no. mnemonic r/w description [1:0] res reserved reserved. [2] gpio2 r/w if gpio2 is set to input, this regist er reflects the state of the pin. if gpio2 is configured as an output, writing to this register asserts the outp ut high or low depending on the polarity. [3] gpio1 r/w if gpio1 is set to input, this regist er reflects the state of the pin. if gpio1 is configured as an output, writing to this register asserts the outp ut high or low depending on the polarity. [4] gpio2 pol r/w gpio2 polarity bit. set to 0 for active low. set to 1 for active high. [5] gpio1 pol r/w gpio1 polarity bit. set to 0 for active low. set to 1 for active high. [6] gpio2 dir r/w gpio2 direction bit. set to 1 for gpio1 to act as an input, se t to 0 for gpio2 to act as an output. [7] gpio1 dir r/w gpio1 direction bit. set to 1 for gpio1 to act as an input, se t to 0 for gpio1 to act as an output. table 81. register 0x81interrupt status register 4 (power-on default = 0x00) bit no. mnemonic r/w description [2:0] res read-only reserved. [3] peci1 read-only a logic 1 indicates that the peci high or low limit ha s been exceeded by the peci value from peci client address 0x31. this bit is cleared on a read of the sta tus register only if the error condition has subsided. [4] peci2 read-only a logic 1 indicates that the peci high or low limit ha s been exceeded by the peci value from peci client address 0x32. this bit is cleared on a read of the sta tus register only if the error condition has subsided. [5] peci3 read-only a logic 1 indicates that the peci high or low limit ha s been exceeded by the peci value from peci client address 0x33. this bit is cleared on a read of the sta tus register only if the error condition has subsided. [6] i mon read-only a logic 1 indicates that the i mon high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [7] v tt read-only a logic 1 indicates that the v tt high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. table 82. register 0x82interrupt mask register 3 (power-on default = 0x00) 1 bit no. mnemonic r/w description [0] peci0 r/w a logic 1 masks smbalert assertions for out-of-limit conditions on peci0. [1] data r/w a logic 1 masks smbalert assertions for peci data errors. [2] comm r/w a logic 1 masks smbalert assertions for peci communications errors. [3] ovt r/w ovt = 1 masks smbalert for overtemperature therm conditions. [6:4] res r/w reserved. [7] ool r/w ool = 1 masks smbalert assertions when the ool status bit is set. note that the ool mask bit is inde pendent of the individual mask bi ts of interrupt mask 4 register (0x83). therefore, if the intention is to mask smbalert assertions for any of the status register 4 bits, ool must also be masked. 1 if the mask bits in register 0x82 are set, it is also necessary to set the ool mask bit in register 0x75 to ensure the smbalert output is not asserted.
adt7490 rev. 0 | page 72 of 76 table 83. register 0x83interrupt mask register 4 (power-on default = 0x00) 1 bit no. mnemonic r/w description [2:0] res r/w reserved. [3] peci1 r/w a logic 1 masks alert assertions for out-of-limit conditions on peci1. [4] peci2 r/w a logic 1 masks alert assertions for out-of-limit conditions on peci2. [5] peci3 r/w a logic 1 masks alert assertions for out-of-limit conditions on peci3. [6] i mon r/w a logic 1 masks alert assertions for out-of-limit conditions on i mon . [7] v tt r/w a logic 1 masks alert assertions for out-of-limit conditions on v tt . 1 if the mask bits in register 0x83 are set, it is also necessary to set the ool mask bit in register 0x82 to ensure the smbalert output is not asserted. table 84. v tt , i mon limit registers register address r/w 1 description power-on default 0x84 r/w v tt low limit 0x00 0x85 r/w i mon low limit 0x00 0x86 r/w v tt high limit 0xff 0x87 r/w i mon high limit 0xff 1 these registers becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subs equent attempts to wr ite to these registers fail. table 85. register 0x88peci configuratio n register 2 (power-on default = 0x00) bit no. mnemonic r/w 1 description [2:0] res r/w reserved. [3] dom3 r/w cpu domain count information. set to 0 indicates th at cpu 4 associated with the peci3 reading has a single domain (default). set to 1 indicates that the system cpu4 contains two domains. [4] dom2 r/w cpu domain count information. set to 0 indicates th at cpu 3 associated with the peci2 reading has a single domain (default). set to 1 indicates that the system cpu3 contains two domains. [5] dom1 r/w cpu domain count information. set to 0 indicates th at cpu 2 associated with the peci1 reading has a single domain (default). set to 1 indicates that the system cpu2 contains two domains. [7:6] #cpu r/w cpu count. these bits indicate the number of cpus in the system, which provide peci thermal information to the adt7490. 00 = 1 cpu (default); indicates that peci0 data is available from cpu 1 at address 0x30. 01 = 2 cpus; indicates that peci0 data is availabl e from cpu1 at address 0x30 and peci1 data is available from cpu 2 at address 0x31. 10 = 3 cpus; indicates that peci0 data is available fr om cpu1 at address 0x30, peci1 data is available from cpu 2 at address 0x31 and peci2 data is available from cpu 3 at address 0x32. 11 = 4 cpus; indicates that peci0 data is available fr om cpu1 at address 0x30, peci1 data is available from cpu 2 at address 0x31, peci2 data is availabl e from cpu 3 at address 0x32 and peci3 data is available from cpu 4 at address 0x33. 1 this register becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subseq uent attempts to writ e to this register fail. table 86. operating point registers 1, 2 register address r/w 3 description power-on default 0x8a r/w peci operating point register 0xfb 0x8b r/w remote 1 operating point register (default = 100c). 0x64 0x8c r/w local temperature operating point register (default = 100c). 0x64 0x8d r/w remote 2 operating point register (default = 100c). 0x64 1 these registers set the target operating point fo r each temperature channel when the dynamic t min control feature is enabled. 2 the fans being controlled are adjusted to mai ntain temperature about an operating point. 3 this register becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subseq uent attempts to writ e to this register fail.
adt7490 rev. 0 | page 73 of 76 table 87. register 0x8edynamic t min control register 1 (power-on default = 0x00) bit no. mnemonic r/w 1 description [0] cyr2 r/w msb of 3-bit remote 2 cycle value. the other two bits of the code reside in the dynamic t min control register 2 (0x8f). these three bits define the delay time between making subsequent t min adjustments in the control loop in terms of the number of monitoring cycles. the system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. [1] v ccp lo r/w v ccp lo = 1. when the power is supplied from 3.3 v standby and the core voltage (v ccp ) drops below its v ccp low limit value (0x46), the following occurs: status bit 1 in status register 1 is set. smbalert is generated, if enabled. prochot monitoring is disabled. dynamic t min control is disabled. the device is prevented from entering shutdown. everything is re-enabled once v ccp increases above the v ccp low limit. [2] phtr1 read/write phtr1 = 1 copies the remote 1 current temperature to the remote 1 operating point register if therm is asserted. the operating point contains the temperature at which therm is asserted, allowing the system to run as quietly as pos sible without affecting system performance. phtr1 = 0 ignores any therm assertions on the therm pin. the remote 1 operating point register reflects its programmed value. [3] phtl r/w phtl = 1 copies the local channels current temper ature to the local operating point register if therm is asserted. the operating point contains the temperature at which therm is asserted. this allows the system to run as quietly as possible without affecting system performance. phtl = 0 ignores any therm assertions on the therm pin. the local temperature operating point register reflects its programmed value. [4] phtr2 r/w phtr2 = 1 copies the remote 2 current temperature to the remote 2 operating point register if therm is asserted. the operating point contains the temperature at which therm is asserted, allowing the system to run as quietly as possible without affecting system performance. phtr2 = 0 ignores any therm assertions on the therm pin. the remote 2 operating point register reflects its programmed value. [5] r1t r/w r1t = 1 enables dynamic t min control on the remote 1 temperature channel. the chosen t min value is dynamically adjusted based on the current tempera ture, operating point, and high and low limits for this zone. r1t = 0 disables dynamic t min control. the t min value chosen is not adjusted, and the channel behaves as described in the automatic fan control overview section. [6] lt r/w lt = 1 enables dynamic t min control on the local temperature channel. the chosen t min value is dynamically adjusted based on the current tempera ture, operating point, and high and low limits for this zone. lt = 0 disables dynamic t min control. the t min value chosen is not adjusted, and the channel behaves as described in the automatic fan control overview section. [7] r2t r/w r2t = 1 enables dynamic t min control on the remote 2 temperature channel. the chosen t min value is dynamically adjusted based on the current tempera ture, operating point, and high and low limits for this zone. r2t = 0 disables dynamic t min control. the t min value chosen is not adjusted, and the channel behaves as described in the automatic fan control overview section. 1 this register becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subseq uent attempts to writ e to this register fail.
adt7490 rev. 0 | page 74 of 76 table 88. register 0x8fdynamic t min control register 2 (power-on default = 0x00) bit no. mnemonic r/w 1 description [2:0] cyr1 r/w 3-bit remote 1 cycle value. these three bits defi ne the delay time between making subsequent t min adjustments in the control loop for the remote 1 channel in terms of number of monitoring cycles. the system has associated thermal time constants th at need to be found to optimize the response of fans and the control loop. bit code decrease cycle increase cycle 000 8 cycles (1 sec) 16 cycles (2 sec) 001 16 cycles (2 sec) 32 cycles (4 sec) 010 32 cycles (4 sec) 64 cycles (8 sec) 011 64 cycles (8 sec) 128 cycles (16 sec) 100 128 cycles (16 sec) 256 cycles (32 sec) 101 256 cycles (32 sec) 512 cycles (64 sec) 110 512 cycles (64 sec) 1024 cycles (128 sec) 111 1024 cycles (128 sec) 2048 cycles (256 sec) [5:3] cyl r/w 3-bit local temperature cycle value. these three bits define the delay time between making subsequent t min adjustments in the control loop for the local temperature channel in terms of number of monitoring cycles. the system has asso ciated thermal time constants that need to be found to optimize the response of fans and the control loop. bit code decrease cycle increase cycle 000 8 cycles (1 sec) 16 cycles (2 sec) 001 16 cycles (2 sec) 32 cycles (4 sec) 010 32 cycles (4 sec) 64 cycles (8 sec) 011 64 cycles (8 sec) 128 cycles (16 sec) 100 128 cycles (16 sec) 256 cycles (32 sec) 101 256 cycles (32 sec) 512 cycles (64 sec) 110 512 cycles (64 sec) 1024 cycles (128 sec) 111 1024 cycles (128 sec) 2048 cycles (256 sec) [7:6] cyr2 r/w 2 lsbs of 3-bit remote 2 cycle value. the msb of the 3-bit code resides in the dynamic t min control register 1 (register 0x8e). these three bits defi ne the delay time between making subsequent t min adjustments in the control loop for the remote 2 channel in terms of number of monitoring cycles. the system has associated thermal time constants th at need to be found to optimize the response of fans and the control loop. bit code decrease cycle increase cycle 000 8 cycles (1 sec) 16 cycles (2 sec) 001 16 cycles (2 sec) 32 cycles (4 sec) 010 32 cycles (4 sec) 64 cycles (8 sec) 011 64 cycles (8 sec) 128 cycles (16 sec) 100 128 cycles (16 sec) 256 cycles (32 sec) 101 256 cycles (32 sec) 512 cycles (64 sec) 110 512 cycles (64 sec) 1024 cycles (128 sec) 111 1024 cycles (128 sec) 2048 cycles (256 sec) 1 this register becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subseq uent attempts to writ e to this register fail.
adt7490 rev. 0 | page 75 of 76 table 89. register 0x90dynamic t min control register 3 (power-on default = 0x00) bit no. mnemonic r/w 1 description [2:0] res reserved reserved. [5:3] cyp r/w 3-bit peci temperature cycle value. these three bits define the delay time between making subsequent t min adjustments in the control loop for the peci temperature channels in terms of number of monitoring cycles. the system has asso ciated thermal time constants that need to be found to optimize the response of fans and the control loop. bit code decrease cycle increase cycle 000 8 cycles (1 sec) 16 cycles (2 sec) 001 16 cycles (2 sec) 32 cycles (4 sec) 010 32 cycles (4 sec) 64 cycles (8 sec) 011 64 cycles (8 sec) 128 cycles (16 sec) 100 128 cycles (16 sec) 256 cycles (32 sec) 101 256 cycles (32 sec) 512 cycles (64 sec) 110 512 cycles (64 sec) 1024 cycles (128 sec) 111 1024 cycles (128 sec) 2048 cycles (256 sec) [6] phtp r/w phtr1 = 1 copies the peci0 current reading to the peci operating point register if therm is asserted. the operating point contains the temperature at which therm is asserted, allowing the system to run as quietly as possible without affecting system performance. phtr1 = 0 ignores any therm assertions on the therm pin. the peci operating point register reflects its programmed value. [7] peci r/w peci = 1 enables dynamic t min control on the peci temperature channel. the chosen t min value is dynamically adjusted based on the current tempera ture, operating point, and high and low limits for this zone. peci = 0 disables dynamic t min control. the t min value chosen is not adjusted and the channel behaves as described in the automatic fan control overview section. 1 this register becomes read-only when the configuration register 1 (0x40) lock bit is set to 1. any subseq uent attempts to writ e to this register fail. table 90. register 0x94peci0 temperat ure offset (power-on default = 0x00) bit no. r/w 1 description [7:0] r/w allows a temperature offset to be automatically applie d to the peci0 channel measurements. the programmable offset range is from ?63c to +127c with 1c resolution. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect. table 91. register 0x95peci1 temperat ure offset (power-on default = 0x00) bit no. r/w 1 description [7:0] r/w allows a temperature offset to be automatically applie d to the peci1 channel measurements. the programmable offset range is from ?63c to +127c with 1c resolution. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect. table 92. register 0x96peci2 temperat ure offset (power-on default = 0x00) bit no. r/w 1 description [7:0] r/w allows a temperature offset to be automatically applied to the peci2 channel measurements. the programmable offset range is from ?63c to +127c with 1c resolution. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect. table 93. register 0x97peci3 temperat ure offset (power-on default = 0x00) bit no. r/w 1 description [7:0] r/w allows a temperature offset to be automatically applie d to the peci3 channel measurements. the programmable offset range is from ?63c to +127c with 1c resolution. 1 this register becomes read-only when the co nfiguration register 1 (0x40) lock bit is set to 1. any further attempts to write t o this register have no effect.
adt7490 rev. 0 | page 76 of 76 outline dimensions compliant to jedec standards mo-137ae 24 13 12 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.069 0.053 0.010 0.006 0.050 0.016 8 0 0.065 0.049 coplanarity 0.004 0.345 0.341 0.337 0.158 0.154 0.150 0.244 0.236 0.228 figure 63. 24-lead shrink small outline package [qsop] (rq-24) dimensions shown in inches ordering guide model termperature range package description package option adt7490arqz 1 C40c to +125c 24-lead qsop rq-24 adt7490arqz-reel 1 C40c to +125c 24-lead qsop rq-24 ADT7490ARQZ-REEL7 1 C40c to +125c 24-lead qsop rq-24 eval-adt7490ebz 1 evaluation board 1 z = rohs compliant part. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06789-0-7/07(0)

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